Modeling study of ultrathin gate oxides using direct tunneling current and capacitance-voltage measurements in MOS devices

Yang, Ni; Henson, W.K.; Hauser, John R.; Wortman, J. J.

doi:10.1109/16.772492

Cited by 224 publications

(101 citation statements)

References 22 publications

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“…However, the use of such models makes routine device simulation computationally prohibitive. On the other hand, a constant effective mass for electrons in SiO 2 gate region has been used to model experimental DT current with reasonable success [12,13]. Although a few recent studies have focused on estimating m ox in SiO 2 and a few other high-K dielectric materials [14], in the absence of any detailed knowledge about the band structures of the dielectric materials, m ox is still widely treated as a fitting parameter.…”

Section: Resultsmentioning

confidence: 99%

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Accurate modeling of gate capacitance in deep submicron MOSFETs with high-K gate-dielectrics

Hakim

Haque

2004

Solid-State Electronics

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Gate capacitance of metal-oxide-semiconductor devices with ultra-thin high-K gate-dielectric materials is calculated taking into account the penetration of wave functions into the gate-dielectric. When penetration effects are neglected, the gate capacitance is independent of the dielectric material for a given equivalent oxide thickness (EOT). Our selfconsistent numerical results show that in the presence of wave function penetration, even for the same EOT, gate capacitance depends on the gate-dielectric material. Calculated gate capacitance is higher for materials with lower conduction band offsets with silicon. We have investigated the effects of substrate doping density on the relative error in gate capacitance due to neglecting wave function penetration. It is found that the error decreases with increasing doping density. We also show that accurate calculation of the gate capacitance including wave function penetration is not critically dependent on the value of the electron effective mass in the gate-dielectric region.

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Section: Resultsmentioning

confidence: 99%

“…For this reason, we too represent electrons in gate-dielectric region by a constant m ox . We choose m ox ¼ 0:5m 0 in SiO 2 [12,13] as well as in other high-K gate-dielectrics. The effects of the choice of m ox on gate capacitance will be discussed later in this section.…”

Section: Resultsmentioning

confidence: 99%

Accurate modeling of gate capacitance in deep submicron MOSFETs with high-K gate-dielectrics

Hakim

Haque

2004

Solid-State Electronics

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“…Analytical model--WKB approximation 3.1 High-k gate Dielectrics For controlling and avoiding the reliability concern of the direct tunneling current of gate dielectrics the physical thickness must be enhanced. Though ultra thin silicon oxide layer is consumed to produce high electrical field in vertical direction to control SCE and guarantee for sufficient drive current in bulk MOSFET [9,10]. Therefore the electrical width of gate dielectrics should be reduced and physical width must be constant.…”

Section: Iosr Journal Of Electronics and Communication Engineering (Imentioning

confidence: 99%

Analytical Model of Tunneling Current by High Dielectrics and Study of High-k Gate Stack Structure

Mehla¹

2016

IOSR

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“…Accordingly, the number of particles near the dielectric is required, given that the distance between their location and the interface modifies the tunnel probability [6]. The simulated particles are distributed along the whole device and hence the percentage of the ones near the interface (n intf ) is estimated with respect to the total number of particles (n(x, z)):…”

Section: Methodsmentioning

confidence: 99%

Assessment of gate leakage mechanism utilizing Multi-Subband Ensemble Monte Carlo

Medina-Bailón

Sadi

Sampedro

et al. 2017

2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)

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Abstract-The inclusion in advanced device simulators of quantum effects different than standard confinement becomes mandatory to describe device behavior as technology approaches the nanometer scales. This work presents a model to include the gate leakage mechanism considering direct and trap assisted tunneling in Multi-Subband Ensemble Monte Carlo (MS-EMC) simulators. The tool is used for the study of FDSOI and FinFET devices.

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Modeling study of ultrathin gate oxides using direct tunneling current and capacitance-voltage measurements in MOS devices

Cited by 224 publications

References 22 publications

Accurate modeling of gate capacitance in deep submicron MOSFETs with high-K gate-dielectrics

Accurate modeling of gate capacitance in deep submicron MOSFETs with high-K gate-dielectrics

Analytical Model of Tunneling Current by High Dielectrics and Study of High-k Gate Stack Structure

Assessment of gate leakage mechanism utilizing Multi-Subband Ensemble Monte Carlo

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