Modeling Techniques and Verification Methodologies for Substrate Coupling Effects in Mixed-Signal System-on-Chip Designs

Abstract

Abstract-The substrate noise coupling problems in today's complex mixed-signal system-on-chip (MS-SOC) brings a new set of challenges for designers. In this paper, we propose a global methodology that includes an early verification in the design flow as well as a postlayout iterative optimization to deal with substrate noise, and helps designers to achieve a first silicon-success of their chips. An improved semi-analytical modeling technique exploiting the basic behaviors of this noise is developed. This method significantly accelerates the substrate modeling, avoids the dense matrix storage, and, hence, enables the implementation of an iterative noise-immunity optimization loop working at full-chip level. The integration of the methodology in a typical mixed-signal design flow is illustrated and its successful application to achieve a single-chip integration of a transceiver is demonstrated.

Fast Substrate Noise Aware Floorplanning for Mixed Signal SOC Designs

“…As such components can degrade the performance or cause failure by interfering with each other, it has to be optimized during layout planning [1]. A major interference is the substrate noise caused by large amount of switching activities in high speed digital cores to analog/RF components, degrading the reliability and performance of these sensitive analog/mixed signal/RF Intellectual Properties (IPs) [2]. Such substrate noise is becoming a growing concern due to higher clock frequency, more accurate analog precision, deeper technology scaling, and tighter integration of analog blocks with digital blocks [3]- [5].…”

“…Although abundant amount of works have been done in modeling and simulation of substrate noise [2], [3], [5]- [11], none of them are suitable to guide substrate noise optimization in floorplanning due to high computational expense or limited application. Therefore, there is not much in the literature on substrate noise optimization in early floorplanning stage.…”

Fast substrate noise-aware floorplanning with preference directed graph for mixed-signal SOCs

“…A key interference is the substrate noise caused by large amount of switching activities in high speed digital cores, to the analog/RF components. It may degrade the reliability and performance of these sensitive analog/mixed-signal/RF IPs [2]. The problem is becoming a growing concern due to higher clock frequency, more accurate analog precision, deeper technology scaling, and the integration of front-end RF with digital blocks [3]- [5].…”

“…The problem is becoming a growing concern due to higher clock frequency, more accurate analog precision, deeper technology scaling, and the integration of front-end RF with digital blocks [3]- [5]. Many effects that corrupt RF signal such as DC offset, oscillator pulling and pushing, local oscillator leakage can be traced to the substrate-coupled noise [2].…”

“…Although This work is supported in part by SRC under contract 2005-TJ-1321, IBM Faculty Award, and equipment donations from Intel. many works have been done in modeling and simulation of substrate noise [2], [3], [5], [12]- [15], there is not much in the literature on substrate noise optimization in early floorplanning stage. Lin et al [7] proposed an optimization technique that incorporates substrate noise minimization into optimization loops.…”