Modeling the Flip-Chip Wetting Process

Abstract

A numerical model is presented for the portion of the flip-chip joining process where liquid-state solder bumps on the substrate and on the device merge (wet) to form full interconnections. An excellent agreement is demonstrated between calculations and experimental data for the accompanying reduction as a function of time in the device-substrate gap height resulting from the wetting process. The model is based on the detailed description of the random wetting transition of every interconnection in large devices, parametrized by a single parameter describing the wetting dynamics of the solder (including, for instance, the retarding effect of oxidation). This allows the model to be used to systematically study the effect of a number of variables (thermal expansion and heating rates, substrate warpage, spatial distribution of solder bump volumes on the substrate and device, etc.) on the rate of occurrence of important defects that appear during the flip-chip wetting process, such as electrical open (nonwet) or short (bridge) defects.

Application of multi-quality parameter design in the optimization of underfilling process – a case study of a vehicle electronic module

“…Then, the signal is transferred from the chip to the lead frame by a wire bond, which is then packaged into an electronic component, to facilitate the subsequent bonding of the pins of the lead frame to the printed circuit board (PCB) via surface mount technology (SMT). In flip-chip technology, the chip's functioning surface is placed downwards on the substrate and the signal is connected to the substrate using solder bumps, as configured on the underside of the chip (Rangaraj et al, 2017;Sylvestre et al, 2014;Alander et al, 2003). Area arrays, such as the ball grid array (BGA) and chip-scale package (CSP), use solder balls arranged on the substrate bottom to transfer the component signal to the PCB, effectively increasing the functional density of the packaged component.…”