2018 19th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and 2018
DOI: 10.1109/eurosime.2018.8369869
|View full text |Cite
|
Sign up to set email alerts
|

Modeling the influence of mold compound and temperature profile on board level reliability of single die QFN packages

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1
1
1

Citation Types

0
8
0

Year Published

2020
2020
2024
2024

Publication Types

Select...
4
3

Relationship

0
7

Authors

Journals

citations
Cited by 10 publications
(8 citation statements)
references
References 12 publications
0
8
0
Order By: Relevance
“…This results in an RF port structure with a size of 0.32 mm×0.20 mm, which occupies only 3.5% of the chip area. Solder balls with a diameter of 50 μm connect the chip with the metalized bottom layer of dielectric 2 . Due to the cylindrical arrangement of the ground solder balls, a quasicoaxial field distribution is formed, as shown in Fig.…”
Section: A Mmic-to-glass Layermentioning
confidence: 99%
See 2 more Smart Citations
“…This results in an RF port structure with a size of 0.32 mm×0.20 mm, which occupies only 3.5% of the chip area. Solder balls with a diameter of 50 μm connect the chip with the metalized bottom layer of dielectric 2 . Due to the cylindrical arrangement of the ground solder balls, a quasicoaxial field distribution is formed, as shown in Fig.…”
Section: A Mmic-to-glass Layermentioning
confidence: 99%
“…Conventional solutions like quad-flat-no-lead (QFN) [2], [3] suffer from high dielectric losses due to epoxy based mold compounds. Hence, the radiation efficiency of antennas covered by mold compounds is low.…”
Section: Introductionmentioning
confidence: 99%
See 1 more Smart Citation
“…Solder joint reliability in bottom terminated component depends on both the board properties as well as component characteristics such as the die size and mold compound especially to its coefficient of thermal expansion (CTE) as shown in Quad Flat No packages. Thermal cycle profile also has an influence on the board level solder joint reliability [3]. While some believe that voids will act as stress concentrators, reducing the solder joint fatigue life, voids located in the bulk of the solder do not affect thermo-mechanical fatigue life of the solder joint [4].…”
Section: Fig 1 Schematic Of a Semiconductor Package With Different mentioning
confidence: 99%
“…Several studies on board-level reliability uses finite element analysis (FEA) technique [3,[5][6]10,[12][13][14][15][16]. This computer simulation has become popular with solder joint reliability modeling because it enables faster evaluation of design options before the actual semiconductor package is built.…”
Section: Solder Joint Reliabi Modelingmentioning
confidence: 99%