Modelling and Automated Implementation of Optimal Power Saving Strategies in Coarse-Grained Reconfigurable Architectures

Palumbo, Francesca; Fanni, Tiziana; Sau, Carlo; Meloni, Paolo; Raffo, Luigi

doi:10.1155/2016/4237350

Cited by 5 publications

(8 citation statements)

References 39 publications

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“…The estimation is based on two sets of models that determine the static and dynamic consumption of each LR when clock gating or power gating are applied. The proposed models are derived after a single logic synthesis of the baseline CGR system generated by MDC, carried out with commercial synthesis tools from the analysis of the power reports obtained after netlist simulation [55,56].…”

Section: Hybrid Clock/power Gatingmentioning

confidence: 99%

The Multi-Dataflow Composer tool: An open-source tool suite for optimized coarse-grain reconfigurable hardware accelerators and platform design

Fanni

Rubattu

et al. 2021

Microprocessors and Microsystems

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Modern embedded and cyber-physical systems require every day more performance, power efficiency and flexibility, to execute several profiles and functionalities targeting the ever growing adaptivity needs and preserving execution efficiency. Such requirements pushed designers towards the adoption of heterogeneous and reconfigurable substrates, which development and management is not that straightforward. Despite acceleration and flexibility are desirable in many domains, the barrier of hardware deployment and operation is still there since specific advanced expertise and skills are needed. Related challenges are effectively tackled by leveraging on automation strategies that in some cases, as in the proposed work, exploit model-based approaches. This paper is focused on the Multi-Dataflow Composer (MDC) tool, that intends to solve issues related to design, optimization and operation of coarse-grain reconfigurable hardware accelerators and their easy adoption in modern heterogeneous substrates. MDC latest features and improvements are introduced in detail and have been assessed on the so far unexplored robotics application field. A multi-profile trajectory generator for a robotic arm is implemented over a Xilinx FPGA board to show in which cases coarse-grain reconfiguration can be applied and which can be the parameters and trade-offs MDC will allow users to play with.

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Section: Hybrid Clock/power Gatingmentioning

confidence: 99%

The Multi-Dataflow Composer tool: An open-source tool suite for optimized coarse-grain reconfigurable hardware accelerators and platform design

Fanni

Rubattu

et al. 2021

Microprocessors and Microsystems

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“…Paim et al [28] focused on a power-predictive environment for power-aware FIR filter design based on Remez algorithm, which enables fast and power-aware decision even in mathematical design level, reducing the power dissipation and the time-to-market of the chip. Fanni et al [11,29] studied an estimation model of power consumption to identify the regions of the design that can benefit from the application of power saving techniques. Nasirian et al [25] modeled the behaviour of router buffers using queuing theory to evaluate the effect of power gating on the overall power saving and power penalty on network-on-chip.…”

Section: Related Workmentioning

confidence: 99%

“…However, generally speaking, all the mentioned works lack in terms of generality. In the example analyzed above, Paim et al [28] focused on FIR filters, the work presented by Fanni et al [11,29] is valid for coarse-grain virtual reconfigurable systems, and the one from Paim et al [28] for networks-on-chip. Other researchers focused on more generic approaches.…”

Section: Related Workmentioning

confidence: 99%

“…In general, trade-off among complexity of the models and accuracy should be pursued. As an example, in the context of coarse-grained reconfigurable architectures, Fanni et al [11,29] were capable of reaching a good estimation accuracy in the proposed power models, while keeping the design exploration time low. This was performed by combining low level technological information and high level information related to the dataflow representation of the functionality implemented in the architecture.…”

Section: Introductionmentioning

confidence: 99%

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NeuPow

Nasser

Prévotet

et al. 2020

ACM Trans. Des. Autom. Electron. Syst.

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In this paper, we present a new, simple, accurate and fast power estimation technique that can be used to explore the power consumption of digital system designs at an early design stage. We exploit the machine learning techniques to aid the designers in exploring the design space of possible architectural solutions, and more specifically, their dynamic power consumption, which is application, technology, frequency and data stimuli dependent. To model the power and the behavior of digital components, we adopt the Artificial Neural Networks (ANNs), while the final target technology is Application Specific Integrated Circuit (ASIC). The main characteristic of the proposed method, called NeuPow, is that it relies on propagating the signals throughout connected ANN models to predict the power consumption of a composite system. Besides a baseline version of the NeuPow methodology that works for a given predefined operating frequency, we also derive an upgraded version that is frequency aware, where the same operating frequency is taken as additional input by the ANN models. To prove the effectiveness of the proposed methodology, we perform different assessments at different levels. Moreover, technology and scalability studies have been conducted, proving the NeuPow robustness in terms of these design parameters. Results show a very good estimation accuracy with less than 9% of relative error independently from the technology and the size/layers of the design. NeuPow is also delivering a speed-up factor of about 84× with respect to the classical power estimation flow.

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“…System-level power management would help when a low power accelerator is needed, but it requires to be aware of the effectiveness of the applied technique, which in turn may depend on the adopted HLS tool. Some works tried to address the power management at system-level [7][8][9] and in some cases they also tackled design automation for HW acceleration and adaptivity [10,11]. However, to the best of our knowledge, there are no works in the literature that study the mutual impact of the chosen HLS and the adopted the power management strategy.…”

Section: Introductionmentioning

confidence: 99%

Mutual Impact between Clock Gating and High Level Synthesis in Reconfigurable Hardware Accelerators

et al. 2021

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With the diffusion of cyber-physical systems and internet of things, adaptivity and low power consumption became of primary importance in digital systems design. Reconfigurable heterogeneous platforms seem to be one of the most suitable choices to cope with such challenging context. However, their development and power optimization are not trivial, especially considering hardware acceleration components. On the one hand high level synthesis could simplify the design of such kind of systems, but on the other hand it can limit the positive effects of the adopted power saving techniques. In this work, the mutual impact of different high level synthesis tools and the application of the well known clock gating strategy in the development of reconfigurable accelerators is studied. The aim is to optimize a clock gating application according to the chosen high level synthesis engine and target technology (Application Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA)). Different levels of application of clock gating are evaluated, including a novel multi level solution. Besides assessing the benefits and drawbacks of the clock gating application at different levels, hints for future design automation of low power reconfigurable accelerators through high level synthesis are also derived.

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Modelling and Automated Implementation of Optimal Power Saving Strategies in Coarse-Grained Reconfigurable Architectures

Cited by 5 publications

References 39 publications

The Multi-Dataflow Composer tool: An open-source tool suite for optimized coarse-grain reconfigurable hardware accelerators and platform design

The Multi-Dataflow Composer tool: An open-source tool suite for optimized coarse-grain reconfigurable hardware accelerators and platform design

NeuPow

Mutual Impact between Clock Gating and High Level Synthesis in Reconfigurable Hardware Accelerators

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