Modelling and characterization of NAND flash memory channels

Xu, Quan; Gong, Pu; Michael, John; Li, Shancang

doi:10.1016/j.measurement.2015.04.003

Cited by 12 publications

(6 citation statements)

References 9 publications

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“…The PDF of the erased state threshold voltage is (Suh, Lim, Kim, Choi, Koh & Lim, 1995). By the ISPP technique, the threshold-voltage distribution of the k-programmed state is uniform (Dong, Pan, & Zhang, 2014;Xu, Gong, Chen, Michael & Li, 2015), whose PDF is given by…”

Section: Nand Flash Memory Channelmentioning

confidence: 99%

A Nonuniform Reference Voltage Optimization Based on Relative-Precision-Loss Ratios in MLC NAND Flash Memory

Lv¹,

Huang²,

Zhao³

2021

CIS

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In Multi-Level-Cell (MLC) NAND flash memory, cell-to-cell interference (CCI) and retention time have become the main noise that degrades the data storage reliability. To mitigate such noise, a relative precision loss (RPL) nonuniform reference voltage sensing strategy is proposed in this paper. First, based on the NAND flash channel model with CCI and retention noise, we simulate the data storage process of MLC NAND flash by Monte Carlo method, and find that the threshold-voltage of each disturbed storage state shows approximately to be Gaussian distributed. Then, by Gaussian approximation, the distribution of threshold voltage can be estimated easily in mathematics with a little loss. Second, we introduce a concept of log-likelihood ratio (LLR)-based RPL ratio to determine the dominating overlap regions, and then propose a new nonuniform reference voltage sensing strategy. This strategy does not only reduce the memory sensing precision (i.e., the number of reference voltages), but also maintains the reliability of the soft information of NAND flash memory channel output for soft decoding. Third, we implement extensive simulations to verify the performance of the new nonuniform sensing strategy. The BER performances of LDPC codes for different sensing strategies are provided to show that the proposed LLR-based RPL-nonuniform sensing strategy can make a good compromise between memory sensing latency and error-correction performance.

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Section: Nand Flash Memory Channelmentioning

confidence: 99%

A Nonuniform Reference Voltage Optimization Based on Relative-Precision-Loss Ratios in MLC NAND Flash Memory

Lv¹,

Huang²,

Zhao³

2021

CIS

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“…The MLC flash memory channel model in [11] is adopted here. According to [27]- [32], the read voltage of a 2-bit MLC NAND cell can be expressed by…”

Section: System Modelmentioning

confidence: 99%

A Discrete Detection and Decoding of MLC NAND Flash Memory With Retention Noise

Sun

Zheng

2020

IEEE Access

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The retention noise in MLC NAND flash memory has a great impact on reliability and lifetime of devices. How to recover information from the data corrupted by retention noise is a challenging problem. The joint processing of channel estimation, detection and low-density parity-check (LDPC) decoding is an effective method to handle this problem, while which is hindered by the limited computational resource of NAND flash memory devices. This paper proposes a discrete retention-failure recovery method, where the reading system only processes integers. The proposed method consists of two major components referred to binary tree searching (BTS) based channel updating and information bottleneck (IB) based LDPC decoding. In channel updating, the proposed learning based BTS algorithm can acquire reference voltages directly; thus it bypasses the intermediate stage of retention noise parameter estimation. The LDPC decoder is realized by IB based message passing, where node operation is achieved by lookup tables, and the messages passed between nodes are integers. Besides, a dynamic quantization level reduction strategy for IB based decoding is proposed to reduce the memory consumption of lookup tables. Finally, using PEG-constructed regular LDPC code (8000, 7200), the numerical results show that the proposed discrete method has much lower computational complexity and similar performance compared with the conventional method.

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“…Each program step increases the voltage level of a cell by ∆V pp , which is significantly smaller than the actual voltage levels representing memory values. The voltage raise due to a single program step can be modeled [26] by adding a uniform random variable in the range of 0, ∆V pp . The program process that includes a sequence of L program steps is thereby modeled by the sum of L such uniform random variables, giving the well-known Gaussian shaped voltage level distributions, when L 1. , where α is the capacitance ratio between the two cells and ∆V pp is the ISPP voltage step.…”

Section: B Ici Analysismentioning

confidence: 99%

“…Proof: The ICI noise is the sum of L independent random variables U i uniformly distributed over 0, ∆V pp multiplied by the capacitance coupling α [26].…”

Section: B Ici Analysismentioning

confidence: 99%

d-imbalance WOM codes for reduced inter-cell interference in multi-level NVMs

Hemo

Cassuto

2016

2016 IEEE International Symposium on Information Theory (ISIT)

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Abstract-In recent years, due to the spread of multi-level nonvolatile memories (NVM), q-ary write-once memories (WOM) codes have been extensively studied. By using WOM codes, it is possible to rewrite NVMs t times before erasing the cells. The use of WOM codes enables to improve the performance of the storage device, however, it may also increase errors caused by inter-cell interference (ICI). This work presents WOM codes that restrict the imbalance between code symbols throughout the write sequence, hence decreasing ICI. We first specify the imbalance model as a bound d on the difference between codeword levels. Then a 2-cell code construction for general q and input size is proposed. An upper bound on the write count is also derived, showing the optimality of the proposed construction. In addition to direct WOM constructions, we derive closed-form optimal write regions for codes constructed with continuous lattices.On the coding side, the proposed codes are shown to be competitive with known codes not adhering to the bounded imbalance constraint. On the memory side, we show how the codes can be deployed within flash wordlines, and quantify their BER advantage using accepted ICI models.

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Modelling and characterization of NAND flash memory channels

Cited by 12 publications

References 9 publications

A Nonuniform Reference Voltage Optimization Based on Relative-Precision-Loss Ratios in MLC NAND Flash Memory

A Nonuniform Reference Voltage Optimization Based on Relative-Precision-Loss Ratios in MLC NAND Flash Memory

A Discrete Detection and Decoding of MLC NAND Flash Memory With Retention Noise

d-imbalance WOM codes for reduced inter-cell interference in multi-level NVMs

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