Modelling and simulation of subthreshold behaviour of cylindrical surrounding double gate MOSFET for enhanced electrostatic integrity

Verma, Jay Hind Kumar; Haldar, Subhasis; Gupta, Rashmi; Gupta, Mridula

doi:10.1016/j.spmi.2015.09.024

Cited by 17 publications

(6 citation statements)

References 20 publications

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“…In this section, the theoretical and numerical simulation results are presented using Equations (27), (32), (35), and (40). The list of parameters used for the CSDG MOSFETs are given in Table 1.…”

Section: Resultsmentioning

confidence: 99%

“…However, the authors did not consider the subthreshold regime. Verma et al [27] worked on the subthreshold regime of the CSDG MOSFET in which only the threshold voltage was analyzed.The proposed CSDG MOSFET is designed on a hollow concentric cylindrical structure in which a simple analytical channel potential model has been derived at subthreshold regime. The 2D Poisson equation is solved with the EMA as a boundary valued problem to obtain the minimum surface potential.…”

mentioning

confidence: 99%

“…However, the authors did not consider the subthreshold regime. Verma et al [27] worked on the subthreshold regime of the CSDG MOSFET in which only the threshold voltage was analyzed.…”

mentioning

confidence: 99%

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Analytical Performance of the Threshold Voltage and Subthreshold Swing of CSDG MOSFET

Maduagwu¹,

Srivastava²

2019

JLPEA

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In this research work, the threshold voltage and subthreshold swing of cylindrical surrounding double-gate (CSDG) MOSFET have been analyzed. These analyses are based on the analytical solution of 2D Poisson equation using evanescent-mode analysis (EMA). This EMA provides the better approach in solving the 2D Poisson equation by considering the oxide and Silicon regions as a two-dimensional problem, to produce physically consistent results with device simulation for better device performance. Unlike other models such as polynomial exponential and parabolic potential approximation (PPA) which consider the oxide and silicon as one-dimensional problem. Using the EMA, the 2D Poisson equation is decoupled into 1D Poisson equation which represent the long channel potential and 2D Laplace equation describing the impacts of short channel effects (SCEs) in the channel potential. Furthermore, the derived channel potential close-form expression is extended to determine the threshold voltage and subthreshold behavior of the proposed CSDG MOSFET device. This model has been evaluated with various device parameters such as radii Silicon film thickness, gate oxide thickness, and the channel length to analyze the behavior of the short channel effects in the proposed CSDG MOSFET. The accuracy of the derived expressions have been validated with the mathematical and numerical simulation.increases the packing density, and most importantly leads to better controllability of the gate over the channel [17,21]. The gate control results to enhancement of the subthreshold characteristics and greater immunity to SCEs. However, in terms of current drive the CSG MOSFETs have lesser current compared with the DG MOSFET, hence, its extensive use is limited for high performance application [22]. Thus, there is need to improve on the geometric structure of the CSG MOSFET to enhance the current drive, the gate control over the channel and further improve the SCEs immunity at the nanoscale regime.A novel structure, the cylindrical surrounding double gate (CSDG) MOSFET, was proposed by Srivastava et al. [12]. The geometry is similar to that of the CSG MOSFET with an internal core gate. The core gate enhances the channel control and improves the SCEs immunity. Additionally, the device allows for higher packing density and higher volume inversion than DG MOSFETs and CSG MOSFETs [23,24]. The explicit charge model based on the unified charge model was carried out by Srivastava et al. [25,26]. The authors analyzed the channel current for the novel structure to be higher than the single, DG MOSFET, and CSG MOSFET. However, the authors did not consider the subthreshold regime. Verma et al. [27] worked on the subthreshold regime of the CSDG MOSFET in which only the threshold voltage was analyzed.The proposed CSDG MOSFET is designed on a hollow concentric cylindrical structure in which a simple analytical channel potential model has been derived at subthreshold regime. The 2D Poisson equation is solved with the EMA as a boundary valued problem to obtain the mi...

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Section: Resultsmentioning

confidence: 99%

mentioning

confidence: 99%

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Analytical Performance of the Threshold Voltage and Subthreshold Swing of CSDG MOSFET

Maduagwu¹,

Srivastava²

2019

JLPEA

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“…This is why many new multiple gate structures such as double-gate (DG) [3], triple-gate (TG) [4], -gate [5], -gate [6], quadruple-gate (QG) and surrounding gate MOSFETs [7,8] have become coveted research topics because of their high gate control ability and their high scaling [6]. Among these developed structures, the cylindrical surrounding-gate (CSG) MOSFET is considered as one of suitable candidates giving the possibility to reduce the SCEs for a specified oxide thickness and channel length [9,10]. To overcome these challenges, junctionless (JL) transistors are suggested [11].…”

Section: Introductionmentioning

confidence: 99%

Channel Length Effect on Subthreshold Characteristics of Junctionless Trial Material Cylindrical Surrounding-Gate MOSFETs with High-k Gate Dielectrics

Lagraf¹,

Djamil²,

Guergouri³

et al. 2019

J. Nano- Electron. Phys.

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The intensive decrease of channel length for a MOS transistor imposes extensive constraints notably for controlling the short channel effects (SCEs) in nanoscale MOSFET. These constraints can degrade the device performance, hence determining the limits of miniaturization of MOSFET in nanoelectronics applications. In order to reduce the degree of SCEs, a number of new architectures have been reported. Due to their higher scaling capabilities, the double-gate (DG) MOSFETs are expected to be maintained in future nanoelectronics applications. However, with the continuous miniaturization other serious challenges related to the maximum power dissipation and the fabrication cost still persist owing to the high cost techniques used for the elaboration of the p-n junctions. Recently, a new design called junctionless MOSFET without source/drain junctions has been proposed to be an excellent alternative to the conventional MOSFET. The major advantage of this structure resides on the enhanced fabrication procedure through the elimination of the p-n junctions. In this work, the impact of channel length and high-k gate dielectrics materials on the subthreshold characteristics of junctionless trial material cylindrical surrounding-gate MOSFETs (JLTMCSG-MOSFETs) with high-k gate dielectrics and trial material (TM) structure has been studied using two-dimensional analytical model. This model is based on the solution of Poisson's equation in continuous cylindrical regions using superposition method, where the Fourier-Bessel series and separation method have been used to obtain the accurate solution. The performance of low power JLTMCSG-MOSFETs is investigated in terms of surface potential distribution, electrical field, subthreshold current, drain induced barrier lowering (DIBL), subthreshold slope (SS) and threshold voltage (Vth). This study is carried out over a wide range of channel lengths and using high-k gate dielectrics. This study confirms that the analytical model used is useful not only for circuit simulations, but also for device design and optimization for both logic and analog RF circuits applications.

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“…In the last decade, modern technology has been concerned with the study of mini components electronic at the nanoscale, especially the Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET) [1]. This is what led to the development of devices and integrated circuits (ICs).…”

Section: Introductionmentioning

confidence: 99%

A high electrical performance of DG-MOSFET transistors in 4H-SiC and 6H-SiC 130 nm technology by BSIM3v3 model

Hebali

Bennaoum

Berka

et al. 2019

Journal of Electrical Engineering

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In this paper, the electrical performance of double gate DG-MOSFET transistors in 4H-SiC and 6H-SiC technologies have been studied by BSIM3v3 model. In which the I–V and gm–V characteristics and subthreshold operation of the DGMOSFET have been investigated for two models (series and parallel) based on equivalent electronic circuits and the results so obtained are compared with the single gate SG-MOSFET, using 130 nm technology and OrCAD PSpice software. The electrical characterization of DG-MOSFETs transistors have shown that they operate under a low voltage less than 1.2 V and low power for both models like the SG-MOSFET transistor, especially the series DG-MOSFET transistor is characterized by an ultra low power. The different transistors are characterized by an ultra low OFF leakage current of pA order, very high ON/OFF ratio of and high subthreshold slope of order 0.1 V/dec for the transistors in 6H-SiC and 4H-SiC respectively. These transistors also proved higher transconductance efficiency, especially the parallel DG-MOSFET transistor.

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Modelling and simulation of subthreshold behaviour of cylindrical surrounding double gate MOSFET for enhanced electrostatic integrity

Cited by 17 publications

References 20 publications

Analytical Performance of the Threshold Voltage and Subthreshold Swing of CSDG MOSFET

Analytical Performance of the Threshold Voltage and Subthreshold Swing of CSDG MOSFET

Channel Length Effect on Subthreshold Characteristics of Junctionless Trial Material Cylindrical Surrounding-Gate MOSFETs with High-k Gate Dielectrics

A high electrical performance of DG-MOSFET transistors in 4H-SiC and 6H-SiC 130 nm technology by BSIM3v3 model

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