Modelling of through silicon via and devices electromagnetic coupling

Abouelatta, Mohamed; Dahmani, Rabah; Valorge, Olivier; Calmon, Françis; Gontrand, Christian

doi:10.1016/j.mejo.2010.10.017

Cited by 7 publications

(1 citation statement)

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“…The potential benefits of 3D integration can vary depending on approach; they include multifunctionality, increased performance, reduced power, small form factor, reduced packaging, increased yield and reliability, flexible heterogeneous integration and reduced overall costs. A key study in a recent paper of ourselves [4] comes from the fact that, when, for instance, the MOS bulk-electrode is floating, the bulk potential becomes a function of the substrate perturbations and this affects, for instance, the value of the MOS threshold voltage which in turn varies the MOS drain current.…”

Section: Introductionmentioning

confidence: 99%

Analytical and Numerical Model Confrontation for Transfer Impedance Extraction in Three-Dimensional Radio Frequency Circuits

Valorge¹,

Sun²,

Lorival³

et al. 2012

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3D chip stacking is considered known to overcome conventional 2D-IC issues, using through silicon vias to ensure vertical signal transmission. From any point source, embedded or not, we calculate the impedance spread out; our ultimate goal will to study substrate noise via impedance field method. For this, our approach is twofold: a compact Green function or a Transmission Line Model over a multi-layered substrate is derived by solving Poisson’s equation analytically. The Discrete Cosine Transform (DCT) and its variations are used for rapid evaluation. Using this technique, the substrate coupling and loss in IC’s can be analyzed. We implement our algorithm in MATLAB; it permits to extract impedances between any pair of embedded contacts. Comparisons are performed using finite element methods

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Section: Introductionmentioning

confidence: 99%