Models of access delays in multiprocessor memories

Bucher, Ingrid Y.; Calahan, D. A.

doi:10.1109/71.139201

Cited by 16 publications

(3 citation statements)

References 10 publications

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“…Network performance depends highly on the network traffic, and hence, access to different traffic models is critically important for a thorough analysis of different characteristics of the network architectures, protocols, and implementations. There has been extensive prior research work on traffic models for different networks ranging from the Internet [11] [12], Ethernet [13] [14], wireless LANs [15] to shared-memory-multiprocessor (SMP) networks [16] [17] [18]. These models provide critical insights into the traffic behavior of the corresponding networks.…”

Section: Related Workmentioning

confidence: 99%

A Novel Synthetic Traffic Pattern for Power/Performance Analysis of Network-on-Chips Using Negative Exponential Distribution

Rahmani¹,

Afzali-Kusha²,

Pedram³

2009

Journal of Low Power Electronics

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In this paper, we present an empirically-derived synthetic traffic model based on the Negative Exponential Distribution (NED) for homogenous and heterogeneous Network-on-chips (NoCs) with any dimensionality. Compared to conventional synthetic traffic profiles, this synthetic traffic profile accurately captures key statistical behavior of realistic traces obtained by running different applications on Network-on-chips. To assess the usefulness of this new NoC traffic model, the average packet hops for the proposed traffic profile is compared with those of some synthetic and realistic traffic patterns. The results show that the NED traffic profile has more similarity with the realistic traffic profiles than those of conventional synthetic ones. Adding this traffic profile to the existing profiles, improves the design and characterization of NoCs.

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Section: Related Workmentioning

confidence: 99%

A Novel Synthetic Traffic Pattern for Power/Performance Analysis of Network-on-Chips Using Negative Exponential Distribution

Rahmani¹,

Afzali-Kusha²,

Pedram³

2009

Journal of Low Power Electronics

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“…The probability that a transaction restarts is calculated in the same way as in the silent/static model, given the same con ict rate. The wasted time per transaction now has a truncated exponential distribution: Since a con ict aborts a transaction early, we can not make use of equation (13) to simplify equation (11). (18) Putting these formulae into equation (11) for R c (V ), we nd that R c (V ) = 1?Bc( c) cBc( c) (19) and, U c (V ) = bc cBc( c) 1?Bc( c) (20) We note that if b c (t) has an exponential distribution, then U c = 1.…”

Section: Fixed/fixedmentioning

confidence: 99%

Characterizing the performance of algorithms for lock-free objects

Johnson

1995

IEEE Trans. Comput.

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Concurrent access to shared data objects must be regulated by a concurrency control protocol to ensure correctness. Many concurrency control protocols require that a process set a lock on the data it accesses. Recently, there has been considerable interest in lock-free concurrency control algorithms. Lock-free algorithms o er the potential for better system performance because slow or failed processes do not block fast processes. Process \slowdowns" can occur due to cache line faults, memory and bus contention, page faults, context switching, NUMA architectures, heterogeneous architectures, or di erences in operation execution time. Much work has been done to characterize the performance of locking algorithms, but little has been done to characterize the performance of lock-free algorithms. In this paper, we present a performance model for analyzing lock-free algorithms that studies the e ects of slowdowns on performance. We nd that lock-free algorithms are better than locking algorithms if the slowdowns are transient, but worse if the slowdowns are permanent. One implication of this result is that lock-free concurrent objects are appropriate for UMA architectures, but NUMA architectures require special protocols.

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“…Yuan and Aamodt [9] proposed a hybrid analytical model to predict DRAM access efficiency based on memory trace profiling. Bucher and Calahan [10] modeled the performance of an interleaved common memory of a multiprocessor using queuing and simulation methods. Choi et al [11] presented an analytical model to predict the DRAM performance based on the DRAM timing and memory access pattern parameters.…”

Section: Introductionmentioning

confidence: 99%

Bounding Worst-Case DRAM Performance on Multicore Processors

Ding¹,

Wu²,

Zhang³

2013

Journal of Computing Science and Engineering

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Bounding the worst-case DRAM performance for a real-time application is a challenging problem that is critical for computing worst-case execution time (WCET), especially for multicore processors, where the DRAM memory is usually shared by all of the cores. Typically, DRAM commands from consecutive DRAM accesses can be pipelined on DRAM devices according to the spatial locality of the data fetched by them. By considering the effect of DRAM command pipelining, we propose a basic approach to bounding the worst-case DRAM performance. An enhanced approach is proposed to reduce the overestimation from the invalid DRAM access sequences by checking the timing order of the co-running applications on a dual-core processor. Compared with the conservative approach, which assumes that no DRAM command pipelining exists, our experimental results show that the basic approach can bound the WCET more tightly, by 15.73% on average. The experimental results also indicate that the enhanced approach can further improve the tightness of WCET by 4.23% on average as compared to the basic approach.

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Models of access delays in multiprocessor memories

Cited by 16 publications

References 10 publications

A Novel Synthetic Traffic Pattern for Power/Performance Analysis of Network-on-Chips Using Negative Exponential Distribution

A Novel Synthetic Traffic Pattern for Power/Performance Analysis of Network-on-Chips Using Negative Exponential Distribution

Characterizing the performance of algorithms for lock-free objects

Bounding Worst-Case DRAM Performance on Multicore Processors

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