Models to relate wafer geometry measurements to in-plane distortion of wafers

Turner, Kevin T.; Vukkadala, Pradeep; Sinha, Jaydeep K.

doi:10.1117/1.jmm.15.2.021404

Cited by 4 publications

(2 citation statements)

References 8 publications

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“…Figure 3a shows the freestanding shape data from the bonded wafer pair. The shape data is then converted into distortion using the principles in [4]. The results shown in Figure 3b is the total distortion along the bond interface.…”

Section: Relationship Between Post-bond Distortion and Overlaymentioning

confidence: 99%

Overlay performance in permanent bonded wafer integration schemes

Belyansky

Netzband

et al. 2023

Metrology, Inspection, and Process Control XXXVII

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Several next generation integration schemes – e.g. for 3D stacked transistors, backside power distribution, and advanced packaging involve permanent wafer bonding steps and drive to sub-10nm overlay requirements post bonding. Distortion during wafer bonding is a major determinant of best achievable overlay between post to pre bonding lithography layers. Here, we investigate correlations between wafer bonding process and post bonding overlay performance through a combination of experiment and modelling. We use a custom test vehicle to collect wafer distortion data from pre- and post-bond processes, as well as overlay data after the post-bond processing steps (anneal and thin). The results establish direct relationships between incoming wafer distortion, bonder-induced distortion and post-bond lithography overlay to a pre-bond level. We also use the experimental results to validate a wafer bonding simulation model to further physical explanation of process-induced distortion. The experiment results will enable advanced wafer bonding process controls to optimize distortion and scanner overlay to meet technology targets. The results will also help guide hardware design to improve distortion fingerprints to best improve scanner overlay, as well as address the distortion challenges from incoming wafers.

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Section: Relationship Between Post-bond Distortion and Overlaymentioning

confidence: 99%

Overlay performance in permanent bonded wafer integration schemes

Belyansky

Netzband

et al. 2023

Metrology, Inspection, and Process Control XXXVII

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“…The relationship between wafer shapes and in-plane distortion (IPD) of a single wafer is well known [1,2]. For a single wafer, the IPD is directly correlated to the slope of its freestanding shape.…”

Section: Introductionmentioning

confidence: 99%

Investigation of Post-Bond Distortion in Direct Wafer Bonding

Nagata

Kohama

et al. 2020

ECS Trans.

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Direct wafer bonding process is used in semiconductor manufacturing for heterogeneous integration of devices. When two silicon wafers are directly bonded together, the alignment along the bonded interface is critical to device performance and yield. This paper studies the relative alignment, or post-bond distortion, of a direct wafer bonding process using finite element simulation method. The methodology of constructing a 2D axisymmetric model to calibrate a 3D model is discussed. The simulation results showed that the post-bond distortion was sensitive to upper wafer pre-bond shapes and does not depend on lower wafer shapes. The simulation models enable reduced hardware development costs and time.

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