Abstract. Process-induced overlay errors are a growing problem in meeting the ever-tightening overlay requirements for integrated circuit production. Although uniform process-induced stress is easily corrected, nonuniform stress across the wafer is much more problematic, often resulting in noncorrectable overlay errors. Measurements of the wafer geometry of free, unchucked wafers give a powerful method for characterization of such nonuniform stress-induced wafer distortions. Wafer geometry data can be related to in-plane distortion of the wafer pulled flat by an exposure tool vacuum chuck, which in turn relates to overlay error. This paper will explore the relationship between wafer geometry and overlay error by the use of silicon test wafers with deliberate stress variations, i.e., engineered stress monitor (ESM) wafers. A process will be described that allows the creation of ESM wafers with nonuniform stress and includes many thousands of overlay targets for a detailed characterization of each wafer. Because the spatial character of the stress variation is easily changed, ESM wafers constitute a versatile platform for exploring nonuniform stress. We have fabricated ESM wafers of several different types, e.g., wafers where the center area has much higher stress than the outside area. Wafer geometry is measured with an optical metrology tool. After fabrication of the ESM wafers including alignment marks and first level overlay targets etched into the wafer, we expose a second level resist pattern designed to overlay with the etched targets. After resist patterning, relative overlay error is measured using standard optical methods. An innovative metric from the wafer geometry measurements is able to predict the process-induced overlay error. We conclude that appropriate wafer geometry measurements of in-process wafers have strong potential to characterize and reduce process-induced overlay errors.

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Material removal uniformity during chemical mechanical polishing (CMP) for IC fabrication processes such as shallow trench isolation has previously been shown to be affected by nanotopography (NT) of the wafer frontside (pattern surface). NT is the high frequency height variations of the wafer surface within spatial wavelengths from 0.2 to 20 mm. However, the effect of other topography information such as wafer backside NT and the relatively lower frequency wafer shape on CMP have not been addressed sufficiently. In the present work, the effect of wafer geometry of current and advanced generation wafers on CMP material removal uniformity are investigated using numerical simulations of the CMP process. Specifically, a finite-element based mechanics model was developed and used in conjunction with a wear model based on Preston's equation to simulate the material removal process during CMP. The results demonstrate that the impact of backside NT depends on the stiffness of the CMP backplate (carrier). Simulation results also suggest that higher order wafer shape components can affect CMP results. As technology advances it may be important to control frontside and backside NT as well as higher-order wafer shape in order to reduce their contributions to non-uniform material removal during CMP and the associated yield impact on the integrated circuits that will be manufactured on these substrates.