Impact of Wafer Geometry on CMP for Advanced Nodes

Vukkadala, Pradeep; Turner, Kevin T.; Sinha, Jaydeep K.

doi:10.1149/1.3615988

Cited by 15 publications

(4 citation statements)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Otherwise, it has been shown that the across-wafer CMP material removal uniformity also depends on wafer geometry features such as wafer shape, nanotopography which is different from the design pattern topography. [32][33][34] However, the model could not include all the factors which affect the contact pressure. Therefore, the complicated contact problem is ECS Journal of Solid State Science and Technology, 3 (4) P60-P74 (2014) P63 simplified in order to quantify the contact pressure distribution on the feature scale.…”

Section: Modelingmentioning

confidence: 99%

An Aluminum Gate Chemical Mechanical Planarization Model for HKMG Process Incorporating Chemical and Mechanical Effects

Chen

2014

ECS J. Solid State Sci. Technol.

View full text Add to dashboard Cite

In this work, a new aluminum gate chemical mechanical planarization (CMP) model is proposed in high-k metal gate (HKMG) process for controlling and simulating the metal gate height variation. It systematically captures the effects of mechanical abrasion and concentrations of different types of chemical reagents on material removal rate and surface height evolution. Based on the fundamentals of steady-state oxidation reaction and etched removal in addition to mechanical abrasion, the combinational synergistic interaction is described by separate kinetic parameters such as process parameters, pad properties and slurry chemistry. It can be seen that the removal rate and the coupled effects of the chemical additives are determined from a closed-form equation, making use of the concepts of chemical mechanical equilibrium, chemical kinetics and contact mechanics. The model prediction results show good agreement with the collected experimental data. The metal gate dishing post-Al-CMP is found to increase with increasing the pattern density when the line space is fixed. The dishing value increases with increasing the pattern density up to a certain maximum and then it decreases for a fixed pitch. The present model can be adopted to analyze the influence of the design pattern structures, slurry properties, pad characteristics and polishing conditions on removal rate and wafer surface evolution. The governing equation of aluminum removal and dishing effect reveal some insights into the polishing process and can be used for assisting in HKMG test pattern design and performing the sensitivity analyzes of operating parameters on surface topography during Al-CMP.With the steady shrinkage of the feature size and device geometry of modern integrated circuits (ICs), chemical mechanical planarization (CMP) has emerged as one of the most important solution for surface local and global planarization. Aluminum metal CMP (Al-CMP) process was once a key solution to form the Al damascene interconnects in back-end-of-line (BEOL) application. 1,2 However, due to the low resistivity and better reliability performance of copper, the Cu damascene approach has eventually taken up the mainstream in BEOL interconnect structures.In recent years, the introduction of high-k metal gate (HKMG) structure has enabled the resumption of Moore's Law at the 45/32 nm nodes, when conventional Poly/SiON gate stacks run out of steam. HKMG technology which adopts a replacement metal gate (RMG) approach promises to enable conventional scaling of the transistor as well as reduced stand-by power. Intel had the first 45 nm HKMG processor in volume production in 2007 and most of the foundries introduce HKMG to fabricate their 32/22 nm devices and products. 3 Correspondingly, poly opening polish (POP) processing before dummy poly removed and Al-CMP implementation after work function metal deposited, have been developed to fabricate the HKMG products. 4,5 During the Al metal gate CMP process, the combinational effect of the polishing pad, abrasive particles and chemi...

show abstract

Section: Modelingmentioning

confidence: 99%

An Aluminum Gate Chemical Mechanical Planarization Model for HKMG Process Incorporating Chemical and Mechanical Effects

Chen

2014

ECS J. Solid State Sci. Technol.

View full text Add to dashboard Cite

show abstract

“…Detailed definitions of the wafer geometry of Si wafers are specified by an SEMI standard. 5 Wafer geometry can be classified into components 6 that span different ranges of spatial wavelengths (λ). For example, roughness of a wafer is defined by very high frequency variations with λ < 0.2 mm, followed by nanotopography (NT) variations with λ ranging from a few tenths of a mm to 20 mm.…”

Section: Relationship Between Wafer Geometry Andmentioning

confidence: 99%

Characterization of wafer geometry and overlay error on silicon wafers with nonuniform stress

Brunner

Menon

Wong

et al. 2013

J. Micro/Nanolith. MEMS MOEMS

Self Cite

View full text Add to dashboard Cite

Abstract. Process-induced overlay errors are a growing problem in meeting the ever-tightening overlay requirements for integrated circuit production. Although uniform process-induced stress is easily corrected, nonuniform stress across the wafer is much more problematic, often resulting in noncorrectable overlay errors. Measurements of the wafer geometry of free, unchucked wafers give a powerful method for characterization of such nonuniform stress-induced wafer distortions. Wafer geometry data can be related to in-plane distortion of the wafer pulled flat by an exposure tool vacuum chuck, which in turn relates to overlay error. This paper will explore the relationship between wafer geometry and overlay error by the use of silicon test wafers with deliberate stress variations, i.e., engineered stress monitor (ESM) wafers. A process will be described that allows the creation of ESM wafers with nonuniform stress and includes many thousands of overlay targets for a detailed characterization of each wafer. Because the spatial character of the stress variation is easily changed, ESM wafers constitute a versatile platform for exploring nonuniform stress. We have fabricated ESM wafers of several different types, e.g., wafers where the center area has much higher stress than the outside area. Wafer geometry is measured with an optical metrology tool. After fabrication of the ESM wafers including alignment marks and first level overlay targets etched into the wafer, we expose a second level resist pattern designed to overlay with the etched targets. After resist patterning, relative overlay error is measured using standard optical methods. An innovative metric from the wafer geometry measurements is able to predict the process-induced overlay error. We conclude that appropriate wafer geometry measurements of in-process wafers have strong potential to characterize and reduce process-induced overlay errors.

show abstract

“…Since the introduction of nanotopography metrics, the surface topography of incoming wafers has improved tremendously, which has driven a significant enhancement of CMP and lithography performance. [10][11][12][13][14][15][16] z E-mail: jaydeep.sinha@kla-tencor.com; joann.q.qiu@intel.com Historically, the edge dies on a wafer always yield lower compared to the center dies. To maximize the edge die yield, the wafer edge geometry characteristics need to be well understood.…”

mentioning

confidence: 99%

Local Wafer Shape Characterization

Qiu

Veeraraghavan

Sinha

2015

ECS J. Solid State Sci. Technol.

Self Cite

View full text Add to dashboard Cite

The shape of a silicon wafer is one of the key wafer characteristics. It is not only impacted by wafering and epitaxial processes but also highly modulated by device manufacturing processes, such as film deposition, CMP, lithography, and thermal process. Wafer shape can be best described and visualized by a complex 3D contour map, which contains both global (low spatial frequency) and local (high spatial frequency) wafer shape components. Unfortunately, the 3D contour map is not practical to guide wafer shape control in high volume production. To quantify and control the wafer shape, two global shape metrics, bow and warp, have been used for a few decades. These two metrics, however, are too simplified to capture local wafer shape. In this study, the limitations of traditional global shape metrics, bow and warp, are addressed, and different global and local shape metrics are explored. A novel shape metric of Site Slope-Radial Range (SSRR) reveals unique local wafer shape characteristics in the slope domain and may help us to better understand the impact of local wafer shape to device manufacturing processes, particularly lithography and CMP.

show abstract

Impact of Wafer Geometry on CMP for Advanced Nodes

Cited by 15 publications

References 17 publications

An Aluminum Gate Chemical Mechanical Planarization Model for HKMG Process Incorporating Chemical and Mechanical Effects

An Aluminum Gate Chemical Mechanical Planarization Model for HKMG Process Incorporating Chemical and Mechanical Effects

Characterization of wafer geometry and overlay error on silicon wafers with nonuniform stress

Local Wafer Shape Characterization

Contact Info

Product

Resources

About