Modern Architectures for Embedded Reconfigurable Systems — A Survey

Abstract

Reconfigurable systems, exploiting a mixture of the traditional CPU-centric instruction-stream-based processing with the decentralized parallel application-specific data-dominated processing, provide a drastically higher performance and lower power consumption than the traditional CPU-centric systems. They do it at much lower costs and shorter times to market than the not reconfigurable hardware solutions. They also provide the flexibility that is often required for engineering of modern robust and adaptive systems. Due to their heterogeneity, flexibility and potential for highly optimized application-specific instantiation, the reconfigurable computing (RC) systems are adequate for a very broad class of applications across different industry sectors. In this paper, the basic definitions, concepts and features of reconfigurable systems are discussed, as well as their role, purposes they serve and applications that can significantly benefit from them. Also, a comparison of the hardwired systems, RC systems and CPU-centric systems is made, and some main concepts of an effective and efficient reconfigurable computing are discussed. Subsequently, the classification of the RC systems is introduced and their various architecture classes are overviewed. This is followed by a discussion of some major drivers and requirements of the recent and future developments in the modern RC system area, and an overview of the recent and future development trends in the RC architectures. The reconfigurable system area is a very promising, but quite a new field. New opportunities have been opened for this field through introduction of the system-on-a-chip technology, and a big progress has been made in the recent years. Many different reconfigurable devices and computers became commercially available. Nevertheless, multiple aspects of the RC systems, their development and their supporting tools still belong to the open research or development topics.

A framework for automatic custom instruction identification on multi-issue ASIPs

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