Modular 128-Channel $\Delta$ - $\Delta \Sigma$ Analog Front-End Architecture Using Spectrum Equalization Scheme for 1024-Channel 3-D Neural Recording Microsystems

Park, Sung-Yun; Cho, Jihyun; Na, Kyounghwan; Yoon, Euisik

doi:10.1109/jssc.2017.2764053

Cited by 77 publications

(34 citation statements)

References 37 publications

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“…The rapidly multiplexed acquisition approach is particularly well suited for high channel count microelectrode arrays, where active circuitry is integrated with the device through homogenous fabrication [ 15 , 19 , 25 ] or advanced heterogeneous approaches [ 29 , 60 , 61 ]. The technique in itself does not address interconnect limitations that arise when adopting headstage recording architectures where active circuits (chips) are connected to electrode arrays through standard printed circuit boards and connectors (i.e., not fully implantable) [ 3 , 4 , 5 ].…”

Section: Discussionmentioning

confidence: 99%

Acquisition of Neural Action Potentials Using Rapid Multiplexing Directly at the Electrodes

et al. 2018

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Neural recording systems that interface with implanted microelectrodes are used extensively in experimental neuroscience and neural engineering research. Interface electronics that are needed to amplify, filter, and digitize signals from multichannel electrode arrays are a critical bottleneck to scaling such systems. This paper presents the design and testing of an electronic architecture for intracortical neural recording that drastically reduces the size per channel by rapidly multiplexing many electrodes to a single circuit. The architecture utilizes mixed-signal feedback to cancel electrode offsets, windowed integration sampling to reduce aliased high-frequency noise, and a successive approximation analog-to-digital converter with small capacitance and asynchronous control. Results are presented from a 180 nm CMOS integrated circuit prototype verified using in vivo experiments with a tungsten microwire array implanted in rodent cortex. The integrated circuit prototype achieves <0.004 mm2 area per channel, 7 µW power dissipation per channel, 5.6 µVrms input referred noise, 50 dB common mode rejection ratio, and generates 9-bit samples at 30 kHz per channel by multiplexing at 600 kHz. General considerations are discussed for rapid time domain multiplexing of high-impedance microelectrodes. Overall, this work describes a promising path forward for scaling neural recording systems to numbers of electrodes that are orders of magnitude larger.

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Section: Discussionmentioning

confidence: 99%

Acquisition of Neural Action Potentials Using Rapid Multiplexing Directly at the Electrodes

et al. 2018

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“…The FOM W represents the amount of invested energy in the readout architecture and has been recently used to compare neural recording interfaces for action potentials [42]. As it can be seen in Table I, the proposed ECoG readout achieves an excellent power-efficiency of 4.37 pJ/conversionstep and 14.33-ENOB.…”

Section: Discussionmentioning

confidence: 99%

“…However, the presented chip prototype has a large area consumption compared to the state-of-the-art, primarily due to the sampling capacitors in the first high-pass filter. Although if we calculate the product of the FOM W and area, which is a metric that has been recently introduced in [42], the proposed architecture has a moderate utilization of both power and area. On the other hand, the input referred noise (IRN) is also comparatively higher due to the discretetime operation of the ∆Σ loop filter.…”

Section: Discussionmentioning

confidence: 99%

A 14-ENOB Delta-Sigma-Based Readout Architecture for ECoG Recording Systems

Ivanisevic

Rodriguez

Rusu

2018

IEEE Trans. Circuits Syst. I

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Abstract-This paper presents a delta-sigma based readout architecture targeting electrocortical recording in brain stimulation applications. The proposed architecture can accurately record a peak input signal up to 240 mV in a power-efficient manner without saturating or employing offset rejection techniques. The readout architecture consists of a delta-sigma modulator with an embedded analog front-end. The proposed architecture achieves a total harmonic distortion of -95 dB by employing a current-steering DAC and a multi-bit quantizer implemented as a tracking ADC. A system prototype is implemented in a 0.18 µm CMOS triple-well process and has a total power consumption of 54 µW. Measurement results, across ten packaged samples, show approximately 14-ENOB over a 300 Hz bandwidth with an input referred noise of 5.23 µVrms, power-supply/common-mode rejection ratio of 100 dB/98 dB and an input impedance larger than 94 MΩ.

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“…Multichannel neural recording in vivo is an essential electrophysiology tool to understand brain activities [1,2]. To simultaneously record complex activities from multiple neurons in a designated small brain area, multichannel recording amplifiers must be integrated with area-and energy-efficient manners [3][4][5]. For the last decades, integrated circuit design techniques for multichannel neural recording amplifiers to reduce power and area consumptions have been significantly progressed, resulting in ultralow power consumption (a few µW to sub-µW power consumption per channel) and high-density integration (>1000 channels in a few mm 2 silicon areas).…”

Section: Introductionmentioning

confidence: 99%

Compact Continuous Time Common-Mode Feedback Circuit for Low-Power, Area-Constrained Neural Recording Amplifiers

Kwak

Park

2021

Electronics

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A continuous-time common-mode feedback (CMFB) circuit for low-power, area-constrained neural recording amplifiers is proposed. The proposed CMFB circuit is compact; it can be realized by simply replacing passive components with transistors in a low-noise folded cascode operational transconductance amplifier (FC-OTA) that is one of the most widely adopted OTAs for neural recording amplifiers. The proposed CMFB also consumes no additional power, i.e., no separate CMFB amplifier is required, thus, it fits well to low-power, area-constrained multichannel neural recording amplifiers. The proposed CMFB is analyzed in the implementation of a fully differential AC-coupled neural recording amplifier and compared with that of an identical neural recording amplifier using a conventional differential difference amplifier-based CMFB in 0.18 μm CMOS technology post-layout simulations. The AC-coupled neural recording amplifier with the proposed CMFB occupies ~37% less area and consumes ~11% smaller power, providing 2.67× larger output common mode (CM) range without CM bandwidth sacrifice in the comparison.

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Modular 128-Channel $\Delta$ - $\Delta \Sigma$ Analog Front-End Architecture Using Spectrum Equalization Scheme for 1024-Channel 3-D Neural Recording Microsystems

Cited by 77 publications

References 37 publications

Acquisition of Neural Action Potentials Using Rapid Multiplexing Directly at the Electrodes

Acquisition of Neural Action Potentials Using Rapid Multiplexing Directly at the Electrodes

A 14-ENOB Delta-Sigma-Based Readout Architecture for ECoG Recording Systems

Compact Continuous Time Common-Mode Feedback Circuit for Low-Power, Area-Constrained Neural Recording Amplifiers

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