Modular extension of ATE to 5 Gbps

Keezer, D.C.; Minier, D.; Paradis, Michel; Binette, L.

doi:10.1109/test.2004.1387337

Cited by 18 publications

(8 citation statements)

References 10 publications

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“…Using similar modular extension principles in [3], the application specific block is designed to extend signals from the core logic block, however not utilizing critical ATE resources. This allows for increased customization as various ATE enhancements can be developed depending upon specific needs.…”

Section: B Application Specific Logicmentioning

confidence: 99%

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Stretching the limits of FPGA SerDes for enhanced ATE performance

Majid

Keezer

2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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This paper describes a multi-gigahertz test module to enhance the performance capabilities of automated test equipment (ATE), such as high-speed signal generation, loopback testing, jitter injection, etc. The test module includes a core logic block consisting of a high-performance FPGA. It is designed to be compatible with existing ATE infrastructure; connecting to the device under test (DUT) via a device interface board (DIB). The core logic block controls the test module's functionality, thereby allowing it to operate independently of the ATE. Exploiting recent advances in FPGA SerDes, the test module is able to generate very high (multi-GHz) data rates at a relatively low cost. In this paper we demonstrate multiplexing logic to generate higher data rates (up to 10Gbps) and a low-jitter buffered loopback path to carry high speed signals from the DUT back to the DUT. The test module can generate 10Gbps signals with ~32ps (p-p) jitter, while the loopback path adds ~20ps (p-p) jitter to the input signal.

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Section: B Application Specific Logicmentioning

confidence: 99%

“…In [3] we demonstrated modular extension of ATE performance capabilities. In this research, electronic test modules were developed similar to those shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

Stretching the limits of FPGA SerDes for enhanced ATE performance

Majid

Keezer

2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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“…In [11], a test module is designed using standalone mini-testers which consist of a digital logic core (DLC) designed with an FPGA [12][13][14]. This method is suffering from some timing errors duo to XOR multiplexing gates which are known for data dependent jitter (DDJ) in addition to random jitter.…”

Section: Introductionmentioning

confidence: 99%

High speed test interface module using MEMS technology

Kandalaft

Attaran

Rashizadeh

2015

Microelectronics Reliability

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a b s t r a c t At frequencies above a few gigahertz, testing integrated circuits becomes a challenging task. Test signal integrity degradation due to parasitic effects of interconnects and electromagnetic coupling undermine the test results and increase the yield loss of integrated circuits at high speeds. A new test interface module based on MEMS technology is proposed in this paper. High-speed micro test-channels are designed to establish connectivity between the device under test and the tester at the die level. Experimental results indicate that the proposed architecture can be used to test integrated circuits up to 50 GHz without much loss or distortion.

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“…During the past few years we have developed a modular approach for production testing at multiple-GHz rates using conventional automated test equipment (ATE) [1][2][3][4]. The modules have included various configurations of "driver" and "receiver" channels that multiplex low-speed (<1 Gbps) ATE signals up to 6.4 Gbps as needed for device-undertest (DUT) testing.…”

Section: Introductionmentioning

confidence: 99%

MEMS Switches and SiGe Logic for Multi‐GHz Loopback Testing

et al. 2008

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We describe the use of microelectromechanical system (MEMS) switches and SiGe logic devices for both passive and active loopback testing of wide data buses at rates up to 6.4 Gbps per signal. Target applications include HyperTransport, fully buffered DIMM, and PCI Express, among others. Recently introduced MEMS devices provide >7 GHz bandwidth in a very small package (needed to handle wide buses). SiGe logic supports >7 Gbps signals when active shaping of the waveform is required. Each loopback module typically supports between 9 and 16 differential channels. Multiple cards are used to handle applications with very wide buses or multiple ports. Passive cards utilize MEMS for switching between the loopback (self-test) mode and traditional automated test equipment (ATE) source/receiver channels. Future active card designs may provide additional waveform-shaping functions, such as buffering, amplitude attenuation/modulation, deskew, delay adjustment, jitter injection, and so forth. The modular approach permits precalibration of the loopback electronics and easy reconfiguration between debug or characterization testing and high-volume production screening.

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Modular extension of ATE to 5 Gbps

Cited by 18 publications

References 10 publications

Stretching the limits of FPGA SerDes for enhanced ATE performance

Stretching the limits of FPGA SerDes for enhanced ATE performance

High speed test interface module using MEMS technology

MEMS Switches and SiGe Logic for Multi‐GHz Loopback Testing

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