Module diversification: Fault tolerance and aging mitigation for runtime reconfigurable architectures

Zhang, Hongyan; Bauer, Lars; Kochte, Michael A.; Schneider, Eric; Braun, Claus; Imhof, Michael E.; Wunderlich, Hans-Joachim; Henkel, Jörg

doi:10.1109/test.2013.6651926

Cited by 37 publications

(33 citation statements)

References 29 publications

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“…Generating multiple configurations within the same region for balancing stress is proposed in [1,2,7,8]. [1] proposes periodic swapping between two configurations.…”

Section: Related Workmentioning

confidence: 99%

“…[1] proposes periodic swapping between two configurations. [2] presents multiple placements which swap between unused CLBs and used 978-1-4673-9569-4/16/$31.00 ©2016 IEEE 7A-1 (a) Aperiodic checkpoints for 3 years (b) C 1 when t 0 ≤ t < t 1 and C 2 when t 1 ≤ t ones. The swap is local and limited to adjacent used and unused CLBs.…”

Section: Related Workmentioning

confidence: 99%

“…The aforementioned works aim to reduce stress time without considering the impact of temperature on aging rate. Reconfiguration scheme in [2] does not provide any schedule for reconfiguration. Since aging history affects delay degradation, sequentially generating the configurations and scheduling each configuration is necessary to provide effective aging mitigation.…”

Section: Related Workmentioning

confidence: 99%

“…Researchers have proposed various techniques to exploit such flexibility in FPGAs [1][2][3]. This paper focuses on aginginduced delay degradation in FPGA logic and routing resources and presents a physical planning and reconfiguration scheme to reduce aging-rate and delay degradation in FPGA resources.…”

Section: Introductionmentioning

confidence: 99%

“…In system-level design flow for FPGAs, high-level physical planning tools such as floorplanner * This work is partially supported by NSF grant # 0846129 maps each component at block-(e.g., datapath components) or IP-level (e.g., soft processor) on the device. High level physical planning tools are more effective and powerful than placement tools (CLB-level and/or logic level) [1,2,7,8] to migrate thermal hotspots or highly active blocks globally across the chip. Hence, aging mitigation can be achieved more effectively using an aging-aware floorplanner while aging-aware placement tools due to stringent timing constraints of blocks are only limited to swap used and unused resources locally.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Aging-aware high-level physical planning for reconfigurable systems

Ghaderi

Bozorgzadeh

2016

2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)

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Due to advanced silicon technology, reconfigurable system-on-chip devices such as FPGAs are increasingly becoming sensitive to aging effects. This paper presents a high-level physical planning with reconfiguration strategy in order to mitigate the aging-induced delay degradation in FPGA resources. The proposed solution is an offline framework composed of an agingaware floorplanner coupled with a proactive aging-aware reconfiguration policy which generates checkpoints aperiodically for runtime reconfiguration. We consider BTI and HCI aging mechanisms and consider the BTI-based aging recovery during idle periods using aging history map. The experiments demonstrate that sequence of configurations generated by this scheme provides average aging-rate reduction on FPGA resources and application performance by 53.2% and 17.5%, respectively.

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“…Generating multiple configurations within the same region for balancing stress is proposed in [1,2,7,8]. [1] proposes periodic swapping between two configurations.…”

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Aging-aware high-level physical planning for reconfigurable systems

Ghaderi

Bozorgzadeh

2016

2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)

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i-Core: A Runtime-Reconfigurable Processor Platform for Cyber-Physical Systems

Damschen

Rapp

Bauer

et al. 2019

Embedded, Cyber-Physical, and IoT Systems

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Online Test Strategies and Optimizations for Reliable Reconfigurable Architectures

Bauer

Zhang

Kochte

et al. 2020

Dependable Embedded Systems

Self Cite

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Runtime/reconfigurable architectures based on Field-Programmable Gate Arrays (FPGAs) are a promising augment to conventional processor architectures such as Central Processing Units (CPUs) and Graphic Processing Units (GPUs). Since the reconfigurable parts are typically manufactured in the latest technology, they may suffer from aging and environmentally induced dependability threats. In this chapter, strategic online test methods for dependable runtime-reconfigurable architectures as well as cross-layer optimizations for high reliability and lifetime are developed. Firstly, two orthogonal online tests are proposed that ensure reliable configuration of the reconfigurable fabric and aid fault detection. Secondly, a novel design method called module diversification is presented that enables self-repair of the system in case of faults caused by degradation effects as well as single-event upsets in the configuration. Thirdly, a novel stress-aware placement method is proposed that aims for slowing down system degradation by aging effects. The combined methods ensure reliable operation across architectural and gate level and allow to prolong the lifetime of dependable runtime-reconfigurable architectures.

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Module diversification: Fault tolerance and aging mitigation for runtime reconfigurable architectures

Cited by 37 publications

References 29 publications

Aging-aware high-level physical planning for reconfigurable systems

Aging-aware high-level physical planning for reconfigurable systems

i-Core: A Runtime-Reconfigurable Processor Platform for Cyber-Physical Systems

Online Test Strategies and Optimizations for Reliable Reconfigurable Architectures

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