Monitoring test structure for plasma process induced charging damage using charge-based capacitance measurement (PID-CBCM)

Highly effective and versatile test structure for evaluating dielectric properties using flexible pulse generator on chip

“…Hee-Hwan Ji et al and Moonju Cho et al proposed on-chip CP measurement system with an internal RO in order to protect large gate leakage current in an ultra thin gate oxide [8], [9]. We also proposed the modified CP technique in the plasma process induced charging damage CBCM (PID-CBCM) in the previous work [6]. Specifically, proper DC voltage is applied to Well electrode ofDUT (Vb) as (Vb> Vg), here V g is the gate potential of DUT, so that gate capacitor is applied negative voltage effectively.…”

“…Similar to the conventional method using an external pulse generator, this technique enables to measure charge pumping current. [6]. When DC voltage as Vb> Vg (gate potential of DUT) was applied to the well electrode of the DUT, the voltage applied to the gate capacitor was effectively negative.…”

“…First is the "flexible" RO, second is the start-stop pulse control part [5], and third is the "versatile" test functional parts placed in parallel. Test parts, for example, are CBCM circuits, Devices Under Test (DUTs) of CP and PID-CBCM circuits [6]. Special features of it are as follows.…”