2015 IEEE 65th Electronic Components and Technology Conference (ECTC) 2015
DOI: 10.1109/ectc.2015.7159646
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Monolithic integration of III–V HEMT and Si-CMOS through TSV-less 3D wafer stacking

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Cited by 18 publications
(11 citation statements)
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“…Hence, there are cases where non-silicon devices provide better performance and are required in applications where requirements cannot be met with Si. Recently, Si-CMOS and III-V integration has been demonstrated successfully through our well-established wafer bonding and layer transfer technique [1]- [3]. These devices were demonstrated on a CMOS compatible 200mm Si substrate using metalorganic chemical vapor deposition (MOCVD) system which is more suitable for wafer scaling.…”
Section: Introductionmentioning
confidence: 99%
“…Hence, there are cases where non-silicon devices provide better performance and are required in applications where requirements cannot be met with Si. Recently, Si-CMOS and III-V integration has been demonstrated successfully through our well-established wafer bonding and layer transfer technique [1]- [3]. These devices were demonstrated on a CMOS compatible 200mm Si substrate using metalorganic chemical vapor deposition (MOCVD) system which is more suitable for wafer scaling.…”
Section: Introductionmentioning
confidence: 99%
“…Recently, our group has demonstrated the integration of the Si-CMOS and GaAs=Si or GaN=Si on a common 200 mm Si platform through a double-bond layer transfer process. 17,18) In this study, we take a step further to integrate the Si-CMOS, GaAs, and GaN together on a common 200 mm Si platform. By this method, the functionalities of the materials used can be realized on a single Si platform (e.g., GaAs is more suitable for high-frequency HEMT devices, GaN is more suitable on high-power devices, and inexpensive Si is more suitable for digital control circuitry).…”
mentioning
confidence: 99%
“…Owing to the pin-holes and outgassing issues discovered previously, the BOX layer was removed and replaced with PECVD oxide (with densification and CMP) and PECVD Si 3 N 4 (with densification). 17,18) The GaAs=Ge=Si donor wafer was also subjected to the same PECVD oxide and nitride deposition processes. After that, the SOI-handle wafer was bonded to the GaAs=Ge=Si donor wafer.…”
mentioning
confidence: 99%
“…Hence, co-integrating Si with GaN on a single chip may help in achieving high power and high-performance application. The main motivation for integrating GaN and CMOS is due to the superior GaN performance in fast power switching and the high functionality of CMOS logic, reduction in interconnect distance as well as losses, smaller form factor, reduction in power consumption, lower cost, and lower assembling complexity [191,192]. There are two types of GaN and CMOS integration variants on wafer-level namely Monolithic Integration and Heterogeneous Integration (HI).…”
Section: Heterogeneous Integration Of Gan Hemtmentioning
confidence: 99%
“…As shown in Figure 27, a team from Raytheon [198] in the United States successfully demonstrated fabricating GaN HEMTs in windows on SOI wafers containing Si CMOS transistors, with DC and RF performance comparable to GaN HEMTs on SiC substrate, as well as a first GaN-Si CMOS heterogeneously integrated MMIC: GaN amplifier with CMOS gate bias control circuitry (a current mirror) and heterogeneous interconnects, as shown in Figure 28. For heterogeneous integration, wafer bonding is one of the most promising integration approach for integrating group III-V materials and CMOS on Si [191]. Monolithic structure can be done by direct wafer bonding [199] or heteroepitaxy [200].…”
Section: Heterogeneous Integration Of Gan Hemtmentioning
confidence: 99%