Monolithic three‐dimensional integration of aligned carbon nanotube transistors for high‐performance integrated circuits

Abstract

Carbon nanotube field‐effect transistors (CNT FETs) have been demonstrated to exhibit high performance only through low‐temperature fabrication process and require a low thermal budget to construct monolithic three‐dimensional (M3D) integrated circuits (ICs), which have been considered a promising technology to meet the demands of high‐bandwidth computing and fully functional integration. However, the lack of high‐quality CNT materials at the upper layer and a low‐parasitic interlayer dielectric (ILD) makes the reported M3D CNT FETs and ICs unable to provide the predicted high performance. In this work, we demonstrate a multilayer stackable process for M3D integration of high‐performance aligned carbon nanotube (A‐CNT) transistors and ICs. A low‐κ (~3) interlayer SiO2 layer is prepared from spin‐on‐glass (SOG) through processes with a highest temperature of 220°C, presenting low parasitic capacitance between two transistor layers and excellent planarization to offer an ideal surface for the A‐CNT and device fabrication process. A high‐quality A‐CNT film with a carrier mobility of 650 cm2 V–1 s–1 is prepared on the ILD layer through a clean transfer process, enabling the upper CNT FETs fabricated with a low‐temperature process to exhibit high on‐state current (1 mA μm–1) and peak transconductance (0.98 mS μm–1). The bottom A‐CNT FETs maintain pristine high performance after undergoing the ILD growth and upper FET fabrication. As a result, 5‐stage ring oscillators utilizing the M3D architecture show a gate propagation delay of 17 ps and an active region of approximately 100 μm2, representing the fastest and the most compact M3D ICs to date.

Atomic‐scale strain analysis for advanced Si/SiGe heterostructure by using transmission electron microscopy

“…Complementary metal-oxide-semiconductor (CMOS) technology serves as a powerful engine to ignite the explosive growth of information technology, delivering improved device capabilities and higher component densities for integrated circuits (ICs), thus yielding better system performance at lower cost. [1][2][3][4][5] Throughout the past 2 decades of technological development trails, numerous commitment has been dedicated to novel materials and device architectures such as high-κ/metal gate technology, 6,7 strain engineering, 8,9 and silicon-on-insulator (SOI) technology. 10,11 To realize improved electrostatic control and short-channel control, there has been a shift from planar transistors to novel transistor architectures typified by fin field effect transistors (FinFETs), 12 gate-all-around FETs (GAA FETs), 13,14 complementary FETs (CFETs), 15,16 and vertical FETs (VFETs), 17,18 and the emergence of three-dimensional (3D) stacked transistors (NMOS transistors over PMOS transistors) are proposed, vigorously driving the flourishing development of 3D ICs to achieve an unprecedented integration density and broadband communication.…”

“…Complementary metal‐oxide‐semiconductor (CMOS) technology serves as a powerful engine to ignite the explosive growth of information technology, delivering improved device capabilities and higher component densities for integrated circuits (ICs), thus yielding better system performance at lower cost 1–5 . Throughout the past 2 decades of technological development trails, numerous commitment has been dedicated to novel materials and device architectures such as high‐κ/metal gate technology, 6,7 strain engineering, 8,9 and silicon‐on‐insulator (SOI) technology 10,11 .…”

Solution-Processed Carbon Nanotube Field-Effect Transistors Treated by Material Post-Treatment Approaches

“…Due to their unique physical properties, including high carrier mobility, small intrinsic capacitance, large saturation velocity, and atomic thickness, carbon nanotube-based electronics have attracted extensive attention for future electronic digital [1][2][3][4], radiofrequency [5][6][7], flexible [8][9][10], and radiation-hardened devices [11,12]. After decades of development, great progress has been made by academics, such as in wafer-scale materials with 99.99997% purity [13], transistors better than silicon ones with the same feature size [14,15], and the demonstration of all sorts of integrated circuit (IC) [16][17][18], 3D architectures [19][20][21], radio-frequency (RF) amplifiers within the 5G band [5,6], and even industrial foundries [22]. It is worth noting that the recent remarkable achievements are all based on solution-processed CNTs, compared with chemical vapor deposition (CVD)-based CNTs [14,[23][24][25] or other conformal thin film depositions [26][27][28].…”

Road map for, and technical challenges of, carbon-nanotube integrated circuit technology

“…These advantages enable the ‘real’ 3D integration of CNT electronics with various technologies into one chip through ultradense interlayer vias (ILVs, scaling toward sub-100 nm). Recently, a breakthrough has been achieved in M3D CNT ICs utilizing two-layer FETs, which have a comparable performance and a reduced-by-half area with respect to the best planar CNT circuits [ 10 ]. Another promising application is the near-memory computing system, which integrates CNT logic and state-of-the-art memories into one chip to save latency and energy during data movements [ 11 ].…”