Monolithic transformers and their application in a differential CMOS RF low-noise amplifier

Abstract

A 900 MHz low-noise amplifier (LNA) utilizing three monolithic transformers to implement on-chip tuning networks and requiring no external components has been integrated in 2.88 mm 2 in a standard digital 0.6 m CMOS process. A bias current reuse technique is employed to reduce power dissipation, and process-, voltage-, and temperature-tracking biasing techniques are used. At 900 MHz, the LNA dissipates 18 mW from a single 3 V power supply and provides 4.1 dB noise figure, 12.3 dB power gain, 0 0 033.0 dB reverse isolation, and an input 1-dB compression level of 0 0 016 dBm. Analysis and modeling considerations for silicon-based monolithic transformers are presented, and it is shown that a monolithic transformer occupies less die area and provides a higher quality factor than two independent inductors with the same effective inductance in differential applications. I. INTRODUCTION F INE-LINE CMOS technology easily provides high frequency active devices for use in RF applications (e.g., 800 MHz-2.4 GHz), but high quality passive components (e.g., inductors) present serious challenges to integration as exemplified by several recently reported CMOS RF low-noise amplifier (LNA) designs [1]-[4]. Although significant progress toward the integration of high quality inductors including many innovative structures and design techniques has been reported [5]-[9], practical planar monolithic inductors have achieved only moderate performance owing to resistive losses in the metal traces and in the underlying substrate. Monolithic spiral transformers have been used in monolithic microwave integrated circuit and silicon radio-frequency integrated circuit designs to perform impedance matching, signal coupling, phase splitting, etc. Specific applications include low-loss feedback and single-ended-to-differential signal conversion in a 1.9 GHz receiver front end [10], and matching and coupling in an image rejection mixer [11] and in balanced amplifiers [12], [13]. In this paper, we describe a fully differential CMOS 900 MHz LNA that utilizes monolithic transformers [14]. The design is motivated by the fact that an on-chip spiral transformer comprising two coupled inductors occupies less area and Manuscript

A 1–2 GHz high linearity transformer-feedback power-to-current LNA

“…Trade-offs exist between high gain, wide bandwidth and high linearity in transformer design. Concerning the value of k, three layout configurations are widely used in monolithic transformer design: tapped (k * 0.3-0.5), interleaved (k * 0.7) and stacked (or overlay) (k * 0.9) transformers [5,6]. However, none of them is a good candidate for the TF-PI, since, for the same size, the tapped transformer can achieve large turn-ratio and self-inductance at the expense of a low k factor.…”

Characterization, design and modeling of on-chip interleaved transformers in CMOS RFICs

“…Transformers have found extensive applications in RF designs such as impedance transformation/matching, signal coupling, balun implementation, etc. [1][2][3].…”

Vector potential equivalent circuit based on PEEC inversion

“…For each wire segment, the circuit model only contains ḧ within the truncating window of the segment, and is called windowed VPEC model in Table II. We consider a 32-bit bus with eight segments per line and four different windows: (32, 8), (32, 2), (16,2) and (8,2). Furthermore, we apply the normalized model [19] to VPEC (called normalized VPEC model in Table II) , and is zero for non-aligned segments.…”

“…The on-chip inductors are widely used in CMOS RF circuits, such as LNA and VCO [16], [17]. We have applied VPEC model for the single-layer spiral inductor in Fig.…”