More on the $1/{\rm f}^{2}$ Phase Noise Performance of CMOS Differential-Pair LC-Tank Oscillators

Andreani, Pietro; Fard, Ali

doi:10.1109/jssc.2006.884188

Cited by 133 publications

(64 citation statements)

References 13 publications

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“…6. The CMOS LC-VCO architecture with both NMOS and PMOS switch pairs is chosen for its lower power consumption than single-switch-pair oscillator [9]. For the LC-VCO, the resistor-switching for the current control is used, since it contributes less flicker noise than current mirror, and the chip area of the RC filter for the bias circuits is much more reduced.…”

Section: Other Building Blocks Of the Pllmentioning

confidence: 99%

A 2.4 GHz fractional-N PLL with a low-power true single-phase clock prescaler

Xia

Wang

et al. 2017

IEICE Electron. Express

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A 2.4 GHz fractional-N PLL implemented in 65-nm CMOS process is presented in this letter. A TSPC dual-modulus prescaler is proposed to reduce the PLL's power consumption by merging one of the branches of the true single-phase clocked (TSPC) D flip-flops. The measured synthesizer output frequency ranges from 2.16 to 2.7 GHz, and consumes 8 mW from a 1.3 V power supply. The in-band phase noise is −98 dBc/Hz at 100 kHz offset, and −115 dBc/Hz at 1 MHz offset at a carrier frequency of 2.438 GHz. The circuit achieves the RMS jitter of 0.86 ps and figure of merit of −230 dB, with the fractional spurs below −55 dBc.

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Section: Other Building Blocks Of the Pllmentioning

confidence: 99%

A 2.4 GHz fractional-N PLL with a low-power true single-phase clock prescaler

Xia

Wang

et al. 2017

IEICE Electron. Express

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show abstract

“…Recent phase noise theory based on the impulse sensitivity function (ISF) theory of phase noise, together with a linear-time-variant circuit analysis [7], has shown that not only the small-signal transconductance must be considered. The VCO phase noise depends on the large-signal oscillation amplitude, and that is proportional to the bias current and the parallel tank resistance, which varies with frequency.…”

Section: Tank Loss Variationsmentioning

confidence: 99%

Software‐Defined Radio Front Ends

Hueber¹,

Staszewski

2010

Multi‐Mode/Multi‐Band RF Transceivers for Wireless Communications

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The ultimate dream of every software-defined radio (SDR) front-end architect is to deliver a radio-frequency (RF) transceiver that can be reconfigured into every imaginable operating mode, in order to comply with the requirements of all existing and even upcoming communication standards. These include a large range of modes for cellular (2G-2.5G-3G and further), WLAN (802.11a/b/g/n), WPAN (Bluetooth, Zigbee, etc.), broadcasting (DAB, DVB, DMB, etc.), and positioning (GPS, Galileo) functionalities. Obviously, each of them has different center frequency, channel bandwidth, noise levels, interference requirements, transmit spectral mask, and so on. As a consequence, the performances of all building blocks in the transceiver must be reconfigurable over an extremely wide range, requiring ultimate creativity from the SDR designer.Reconfigurability is a requirement for SDR functionality, but often one forgets that it can also be an enabler for low power consumption. Indeed, once flexibility is built into a transceiver, it can be used to adapt the performance of a radio to the actual circumstances instead of those implied by the worst-case situation of the standard. Since linearity, filtering, noise, bandwidth, and so on, can be traded for power consumption in the SDR, a smart controller is able to adapt the radio at runtime to the actual performance required, and hence can reduce the average power consumption of the SDR.In this chapter, several important innovations and concepts are presented that bring this ultimate dream closer to reality. These include circuits for wideband local oscillator (LO) synthesis, multifunctional receiver and transmitter blocks, and novel ADC (analog-to-digital converter) implementations. The result of all this is integrated in the world's first SDR transceiver covering the frequency range from 174 MHz to 6 GHz, implemented in a 1.2-V 0.13-µm CMOS technology.

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“…2, is formed by the classical differential CMOS LC oscillator. Having both pMOS and nMOS cross-coupled pairs does not significantly increase the noise of the oscillator while assuring a higher small signal negative resistance for a given bias current, making the startup of the oscillator more reliable, and achieving a doubled oscillation amplitude (which turns, ideally, into a 6 dB lower phase noise), compared to oscillators with a single switch pair using the same bias current [7]. Thus, this choice results in a more efficient current-reusing LMV cell, compared to the solutions in [5,[8][9][10].…”

Section: Self-oscillating Mixer and Lc Tankmentioning

confidence: 99%

Time-variant analysis and design of a power efficient ISM-band quadrature receiver

Camponeschi

Bevilacqua

Andreani

2010

Analog Integr Circ Sig Process

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In this work a 2.2 GHz quadrature receiver front-end suitable for low-power applications is presented. The low-noise amplifier, the mixer and the voltage-controlled oscillator are merged into a single stage, making the circuit capable of extreme current reuse while keeping it still functional at low supply voltage. A careful linear timevariant analysis is proven to be necessary to accurately predict the conversion gain and the bandwidth of the downconverter. A prototype, implemented in a 90 nm CMOS technology, validates the theoretical analysis, showing 27 dB of downconversion gain over a 14 MHz base-band bandwidth; the noise figure is 13 dB with a flicker corner frequency of 200 kHz; the input-referred 1 dB compression point is -23.7 dBm. The circuit draws only 1.3 mA from a 1.0 V supply.

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More on the $1/{\rm f}^{2}$ Phase Noise Performance of CMOS Differential-Pair LC-Tank Oscillators

Cited by 133 publications

References 13 publications

A 2.4 GHz fractional-N PLL with a low-power true single-phase clock prescaler

A 2.4 GHz fractional-N PLL with a low-power true single-phase clock prescaler

Software‐Defined Radio Front Ends

Time-variant analysis and design of a power efficient ISM-band quadrature receiver

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