More Power Reduction With 3-Tier Logic-on-Logic 3-D ICs

Song, Taigon; Panth, Shreepad; Chae, Yoo-Jin; Lim, Sung Kyu

doi:10.1109/tcad.2016.2550583

Cited by 3 publications

(3 citation statements)

References 14 publications

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“…Embedded microprocessors are mainly evolved from the core CPU in general-purpose computers [11]. Its characteristic is that it has a 32 bit or more processor, with excellent performance, but with it is the high price [12].…”

Section: Computer-aided Research In the Context Of Wireless Communica...mentioning

confidence: 99%

Design and Research of Computer-Aided Translation Teaching Course under the Background of Embedded Microprocessor Wireless Communication

Yuan

Zhu

2022

Scientific Programming

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The background of wireless communication is the background of the current society. On this basis, the use of embedded microprocessors for computer-assisted translation teaching courses can well cultivate the practical abilities of college students and enable them to quickly integrate into the society. In the context of wireless communication, this article conducts the design and research of computer-assisted translation teaching courses based on embedded microprocessors, explores the use of high-tech system to train students in colleges and universities, and promotes the reform of college classrooms. This research is to use computers for assisted translation and embedded microprocessors for related calculations in translation teaching courses in colleges and universities, which can improve students’ learning efficiency to a certain extent. The experimental results show that the concentration of students in computer-assisted teaching is 20% higher than that of students in traditional teaching, and other related data are more than 8% higher. The teaching of computer-assisted translation courses benefits students greatly.

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Section: Computer-aided Research In the Context Of Wireless Communica...mentioning

confidence: 99%

Design and Research of Computer-Aided Translation Teaching Course under the Background of Embedded Microprocessor Wireless Communication

Yuan

Zhu

2022

Scientific Programming

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“…The size of an MIV is negligible compared to the size of typical standard cells, so there is no density cap placed on the MIV placement. The overall resistance and capacitance of an MIV could be assumed to be 2 Ω and 0.1 fF, respectively, with an approximate diameter of 100 nm [11]. The approximate size and parasitic capacitance of the MIVs are comparable to the antennae diode standard cell, which After the partitioning is performed and each cell is assigned a tier, there exist nets that have been spread across multiple tiers.…”

Section: Insertionmentioning

confidence: 99%

“…The individual dies are referred to as tiers and they are made up of a silicon substrate, followed by a device layer with an interconnect layer on the top [2][3][4]. The early 3D designs involved the tiers being fabricated separately and placed on top of each other and connected with the help of vertical interconnects called through-silicon vias (TSVs) [5][6][7][8][9][10][11]. However, there were several disadvantages to the usage of TSVs compared to the utilization of the more recent technology of monolithic inter-tier vias (MIVs).…”

Section: Introductionmentioning

confidence: 99%

Multi-Tier 3D IC Physical Design with Analytical Quadratic Partitioning Algorithm Using 2D P&R Tool

et al. 2021

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In this study, we developed a complete flow for the design of monolithic 3D ICs. We have taken the register-transfer level netlist of a circuit as the input and synthesized it to construct the gate-level netlist. Next, we partitioned the circuit using custom-made partitioning algorithms and implemented the place and route flow of the entire 3D IC by repurposing 2D electronic design automation tools. We implemented two different partitioning algorithms, namely the min-cut and the analytical quadratic (AQ) algorithms, to assign the cells in different tiers. We applied our flow on three different benchmark circuits and compared the total power dissipation of the 3D designs with their 2D counterparts. We also compared our results with that of similar works and obtained significantly better performance. Our two-tier 3D flow with AQ partitioner obtained 37.69%, 35.06%, and 12.15% power reduction compared to its 2D counterparts on the advanced encryption standard, floating-point unit, and fast Fourier transform benchmark circuits, respectively. Finally, we analyzed the type of circuits that are more applicable for a 3D layout and the impact of increasing the number of tiers of the 3D design on total power dissipation.

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Wire Length Characteristics of Multi-Tier Gate-Level Monolithic 3D ICs

Lin

Kim

2019

IEEE Trans. Emerg. Topics Comput.

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More Power Reduction With 3-Tier Logic-on-Logic 3-D ICs

Cited by 3 publications

References 14 publications

Design and Research of Computer-Aided Translation Teaching Course under the Background of Embedded Microprocessor Wireless Communication

Design and Research of Computer-Aided Translation Teaching Course under the Background of Embedded Microprocessor Wireless Communication

Multi-Tier 3D IC Physical Design with Analytical Quadratic Partitioning Algorithm Using 2D P&R Tool

Wire Length Characteristics of Multi-Tier Gate-Level Monolithic 3D ICs

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