More Precise FPGA Power Estimation and Validation Tool (FPEV_Tool) for Low Power Applications

Verma, Gaurav; Khare, Vijay; Kumar, Manish

doi:10.1007/s11277-018-5938-4

Cited by 15 publications

(6 citation statements)

References 16 publications

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“…Verma et al [148] present a power estimation model that improves the Deng's model [149], and is designed using nonlinear regression techniques. For this purpose, they use the power data of different types of digital circuits (described in VHDL) after the synthesis process.…”

Section: ) Modelsmentioning

confidence: 99%

High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks

et al. 2022

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Hardware accelerators based on field programmable gate array (FPGA) and system on chip (SoC) devices have gained attention in recent years. One of the main reasons is that these devices contain reconfigurable logic, which makes them feasible for boosting the performance of applications. High-level synthesis (HLS) tools facilitate the creation of FPGA code from a high level of abstraction using different directives to obtain an optimized hardware design based on performance metrics. However, the complexity of the design space depends on different factors such as the number of directives used in the source code, the available resources in the device, and the clock frequency. Design space exploration (DSE) techniques comprise the evaluation of multiple implementations with different combinations of directives to obtain a design with a good compromise between different metrics. This paper presents a survey of models, methodologies, and frameworks proposed for metric estimation, FPGA-based DSE, and power consumption estimation on FPGA/SoC. The main features, limitations, and trade-offs of these approaches are described. We also present the integration of existing models and frameworks in diverse research areas and identify the different challenges to be addressed. INDEX TERMSComputing models, design space exploration, field programmable gate array (FPGA), system on chip (SoC), power consumption.years (2016-2022) and have been selected based on the topics addressed in this survey. Several papers published before 2016 have been considered because of their contributions to the current literature. C. OUTLINEThe remainder of this paper is organized as follows. Section II briefly presents the most widely used parallel computing models for CPU, GPU, and multicore processors. Section III introduces the FPGA-based reconfigurable hardware accelerator architectures, hardware/software co-design, DSE and metrics, and the techniques to improve latency, area, and power for this technology. In Section IV, we describe previous works on models, methodologies, and frameworks proposed for FPGA/SoC according to their main features: metrics estimation (IV-A), FPGA-based DSE (IV-B), and power consumption estimation (IV-C); and in Section IV-D, we present a summary and discussion. The integration of models and frameworks for FPGA-based reconfigurable hardware accelerators in different research fields is exposed in Section V. Challenges are analyzed in Section VI. Finally, conclusions are presented in Section VII. II. PARALLEL COMPUTING MODELS FOR PERFORMANCE ESTIMATIONComputing models allow to easily analyzing algorithms by simplifying the computational world to a reduced set of parameters that define the cost of arithmetic and memory access operations and communication. These models contribute to the search for efficient algorithms for a given architecture, improving the productivity of designers, programmers, and engineers. A small amount of communication, a small number of operations, and a high degree of parallelism are key points that d...

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Section: ) Modelsmentioning

confidence: 99%

High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks

et al. 2022

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“…Deng's [82] area and power models were recently improved in [84] by considering power optimization technique such as clock gating. The average error obtained for a set of several IPs is decreased to around 3%.…”

Section: Polynomial-based Power Modelsmentioning

confidence: 99%

RTL to Transistor Level Power Modeling and Estimation Techniques for FPGA and ASIC: A Survey

Nasser

Lorandel

Prévotet

et al. 2021

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Power consumption constitutes a major challenge for electronics circuits. One possible way to deal with this issue is to consider it very soon in the design process in order to explore various design choices. A typical design flow often starts with a high-level description of a full system, which imposes to provide accurate models. Power modelling techniques can be employed, providing a way to find a relationship between power and other metrics. Furthermore, it is also important to consider efficient power characterization techniques. The role of this paper is, first, to provide an overview of RTL to transistor level power modelling and estimation techniques for FPGAs and ASICs devices. Second, it aims at proposing a classification of all approaches according to defined metrics, which should help designers in finding a particular method for their specific situation, even if no common reference is defined among the considered works. Index Terms-Power consumption, power modelling, power estimation, high-level power estimation, FPGA, ASIC, tools.. Antifuse Technology (e.g., Actel TM , Quicklogic TM): an antifuse remains in a high-impedance state until it is programmed into a low-impedance or "fused" state (Figure 9.18). This technology can be used only once on one-time programmable (OTP) devices; it is less expensive than the RAM technology.

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“…Model is created based on the resource utilization data. The dynamic power equations obtained are given in ( 4) to (8) [13], [16]. The comparison result of training and testing data sets is given in Table 2.…”

Section: Regression Model For Ram-based Shift Registermentioning

confidence: 99%

Power Estimation of QPSK and BPSK Modulation Systems for FPGAs based on IP Modeling for Wireless Applications

Singh

Verma

Khare

2021

Preprint

Self Cite

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FPGA market has expanded due to its adoption in mobile phones and wearable devices. The communication IP blocks in Field Programmable Gate Array (FPGAs) has made it possible to realize different communication systems. However, in spite of their high performance, FPGAs suffers from high power consumption due to their complex architecture as compared to their ASIC counterpart. This has made power estimation as an important design metric. The existing commercial tools provide the option to estimate the power, but at the cost of longer estimation time as the designs have to follow the complete design cycle. Moreover, literature, mostly focuses on power estimation of individual blocks and power estimation of the complete system is still in infancy stage. Therefore, in this work, Quadrature Phase Shift Keying (QPSK) and Binary Phase Shift Keying (BPSK) modulation systems have been designed that are used in various wireless and satellite communication applications. Further, a new identity is proposed that could evaluate the power of whole system. The QPSK and BPSK systems have been designed via embedded IP and user-defined IP cores. A power estimation model of diverse blocks of QPSK and BPSK modulation systems have been developed based on a supervised machine learning technique using MATLAB R2016b and models are validated against commercial tool. Finally, the power of complete QPSK and BPSK modulation system is estimated using the proposed identity and is also validated for accuracy with reference to Vivado 2014.2 tool targeted to the Zynq family device and state of the art work. It has been seen from the results that the proposed identity outperforms in power estimation of complete systems as compared to existing identities available in literature and is providing aligned results with reference to the commercial tool.

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More Precise FPGA Power Estimation and Validation Tool (FPEV_Tool) for Low Power Applications

Cited by 15 publications

References 16 publications

High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks

High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks

RTL to Transistor Level Power Modeling and Estimation Techniques for FPGA and ASIC: A Survey

Power Estimation of QPSK and BPSK Modulation Systems for FPGAs based on IP Modeling for Wireless Applications

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