Morphology and Integration of Rough Polycrystalline Silicon Films for DRAM Storage Cell Applications

Abstract

This study evaluates the important aspects of deposition and integration of rough polycrystalline silicon films for dynamic random acces memory (DRAM) storage capacitor applications. Electrical performance of rough polycrystalline films is investigated in terms of grain morphology and microstructural control. It is shown that the morphology, roughness, and doping of the films strongly affect the capacitor electrical performance. A strong correlation is observed between the surface roughness measured in terms of reflectance and the electrical area enhancement factor (AEF) of the films. Leakage current performance of rough and control/smooth electrode devices incorporating NO dielectric is evaluated. The results demonstrate that the leakage current density of the devices with rough electrode is less than the AEF times the leakage current density of the devices with control polysilicon electrode. Various integration approaches to fabricate the rough polysilicon storage electrode are examined. Lower thermal budget processing sequences are shown to be viable options. Rapid thermal based doping and dopant activation anneal processes are demonstrated as alternatives to high temperature furnace annealing sequences. Capacitance‐voltage data is presented with AEF and dopant depletion analysis for devices incorporating lower thermal budget sequences. It is shown that phosphine gas‐doping of the rough polysilicon electrode increases the AEF by 17% as a consequence of the doping process. © 1999 The Electrochemical Society. All rights reserved.