MOS RF Reliability Subject to Dynamic Voltage Stress—Modeling and Analysis

Yu, Chuanzhao; Yuan, J.S.

doi:10.1109/ted.2005.852546

Cited by 48 publications

(18 citation statements)

References 30 publications

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“…Previous works about the reliability of MOSFETs only focused on the DC stress, or a dynamic stress at lower frequency 5, 6 . However, these do not reflect the real operation situation of devices which are used in highfrequency and high-power circuits for wireless communication systems.…”

Section: Introductionmentioning

confidence: 99%

Degeneration of CMOS Power Cells After Hot-Carrier and Load Mismatch Stresses

Liu

Wang

et al. 2008

IEEE Electron Device Lett.

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In this letter, we investigate the performance degradation of nMOS transistors due to hot-carrier effect and load impedance mismatch. The DC and RF characteristics, such as drain current, threshold voltage, transconductance, output power, and power-added efficiency etc., are affected under hot-carrier effect. With load impedance mismatch, the transistors experience the reflected power from load and increase the energy of hot carriers. This effect will make DC and power performances degenerate heavily. In this paper, device characteristics were measured at 5.2 GHz.

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Section: Introductionmentioning

confidence: 99%

Degeneration of CMOS Power Cells After Hot-Carrier and Load Mismatch Stresses

Liu

Wang

et al. 2008

IEEE Electron Device Lett.

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“…The reliability of CMOS transistors due to oxide degradation is especially important to consider in circuits with large voltage swings, like PAs, but the impact of RF stress is not as damaging as DC stress [19], [20]. Two major degradation mechanisms are Fowler-Nordheim tunneling, due to high E across the gate oxide, and Hot Carriers (HC), i.e.…”

Section: B Reliability Considerationsmentioning

confidence: 99%

Analysis of a 5.5-V Class-D Stage Used in $+$30-dBm Outphasing RF PAs in 130- and 65-nm CMOS

Fritzin

Svensson

Alvandpour

2012

IEEE Trans. Circuits Syst. II

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Abstract-This paper presents the design and analysis of a 5.5 V Class-D stage used in two fully integrated watt-level, +32.0 dBm and +29.7 dBm, outphasing RF Power Amplifiers (PA) in standard 130 nm and 65 nm CMOS technologies. The Class-D stage utilizes a cascode configuration, driven by an AC-coupled low-voltage driver, to allow a 5.5 V supply in the 1.2/2.5 V technologies without excessive device voltage stress. RMS electric fields (E) across the gate oxides and the optimal bias point, where the voltage stress is equally divided between the transistors, are computed. At the optimal bias point, the RMS E, the power dissipation of the parasitic drain capacitance of the common-source transistors, and the equivalent on-resistances are reduced by approximately 25 %, 50 %, and 25 %, compared to a conventional cascode (inverter) stage. To the authors' best knowledge, the Class-D PAs presented are among the first fully integrated CMOS outphasing PAs reaching +30 dBm and demonstrate state-of-the-art output power and bandwidth.

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“…In [2][3][4] the impact of breakdown paths on RF Power Amplifier (PA) performance was investigated and the results showed a very high robustness, even to multiple gateoxide breakdown events. If multiple breakdown events can be accurately taken into account for predicting circuit lifetime of such circuits, design guidelines may be relaxed, allowing higher voltage levels and hence higher output power of the PA.…”

Section: Introductionmentioning

confidence: 99%