MOS Technology Drivers

Tonti, W.

doi:10.1109/tdmr.2008.922223

Cited by 11 publications

(5 citation statements)

References 88 publications

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“…1. NMOS structure formation consists of 23 main technological processes, which include high temperature technological processes, among others [6,7]. Simulated NMOS structure is presented in Fig.…”

Section: Selected Nmos Technologymentioning

confidence: 99%

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Simulation of optimization of NMOS structures channel areas technological processes

Kašauskas

Anilionis

2012

2012 13th Biennial Baltic Electronics Conference

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NMOS transistor structures are widely used in IC's. Many manufacturing processes and operations are used in the production process. It is important to choose and deliver technological process (TP) parameters necessary for production for IC design. In this case, the problem addressed is redistribution of structures after a number of TP. So, the optimization of technological manufacturing processes of NMOS structures, and hence the channel area, is important. High-temperature TP (oxidation, diffusion, etc.) have been examined in previous works [4,9]. This paper will focus in the optimization of the channel formation by way of ion implantation (II). A variety of simulations are used for the optimization in the design phase. In this paper, the simulation is performed using ATHENA software package. It is also important to choose and propose the algorithms for optimization of technological processes. This paper offers an optimization algorithm for choosing the modes of II.

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Section: Selected Nmos Technologymentioning

confidence: 99%

“…The basic steps of technological processes are: TP preparation; The gate based on PolySi is formed; The nimpurities are introduced by the (P) ion implantation technological process; Spacer oxide formation; Drain and source area doping with n+ impurities (As); Redistribution of impurities and finalizing operations; [6,7,8]. …”

Section: Selected Nmos Technologymentioning

confidence: 99%

Simulation of optimization of NMOS structures channel areas technological processes

Kašauskas

Anilionis

2012

2012 13th Biennial Baltic Electronics Conference

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“…Overlapping is smaller when lateral impurities distribution is used in technological processes, this helps to reduce extraneous capacities, which reduce IC quick acting [5].…”

Section: Fig 1 Design Of Mos Transistor Structures A) One Diffusionmentioning

confidence: 99%

“…Here i=2, 3,4. So the concentration of impurities in the model would be described evaluating ion dose ĳ (5). But Dual Person model is also suggested (6).…”

Section: Choosing a Modelmentioning

confidence: 99%

Modeling of structures and characteristics in MOS made of ion implantation technological processes

Kašauskas

Anilionis

2010

2010 12th Biennial Baltic Electronics Conference

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MOS transistor structures are widely used in modern integrated circuits (IC). Different manufacturing methods are used. Many problems, such as the length, width of the channel, the overlap of source and drain areas with gate area, the diffusion of impurities after HTTO (high temperature technological operations). The solutions for all these problems are based on the mode of manufacturing processes and its optimization, and that is another problem. In this paper, models are selected and described and the results of modeling are presented. These models evaluate the influence of lateral implantation modes for MOS transistor output characteristics, and the influence for MOS transistor output characteristics. Technological structure problems which appeared in modeling of the exact case MOS are analyzed.

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“…The driver has not limited operating temperature range and keeps the power losses increasing in die temperature over ambient at a very low level. However, the silicon‐on‐insulator (SOI) technology [19], which is more attractive for high‐temperature applications, would need extra costs.…”

Section: Introductionmentioning

confidence: 99%

Research of a novel temperature adaptive gate driver for power metal‐oxide semiconductor

Hua-long

Hua

et al. 2013

IET Power Electronics

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Driving power metal-oxide semiconductor field-effect transistor at high frequency may induce significant switching losses, which have a great proportion in total power losses. Especially in the case of higher temperature, switching losses increased tangibly. A novel temperature adaptive gate driver with low power consumption in a high-temperature environment is proposed for switched-mode power supply by the temperature compensation technique. It has been realised to decrease the switching losses in wide scope temperature, and cannot sacrifice performance of the electromagnetic interferences, by regulating di/dt and dv/dt of switching curve in high temperature. A 0.25 μm, 40 V bipolar-CMOS-DMOS (BCD) process technology is utilised and experimental circuits and results are then presented. Compared with the conventional gate driver, the turn-on loss and turn-off loss of the temperature adaptive gate driver can be reduced, respectively, by 17% and 22%. At present, it has been used in an AC-DC converter to improve work efficiency.

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MOS Technology Drivers

Cited by 11 publications

References 88 publications

Simulation of optimization of NMOS structures channel areas technological processes

Simulation of optimization of NMOS structures channel areas technological processes

Modeling of structures and characteristics in MOS made of ion implantation technological processes

Research of a novel temperature adaptive gate driver for power metal‐oxide semiconductor

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