MOS technology: Trends and challenges in the ULSI era

Shah, A.H.; Yang, Ping

doi:10.1016/s0026-2714(97)00002-4

Cited by 10 publications

(6 citation statements)

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“…Note that this model also neglects the distributions of electrical charge transport, that is, the distribution of electric field, electron density and electron velocity. Device parameters are determined either by the scaling analysis (both constant field scaling and constant voltage scaling [13][14][15]), or the data taken from the literature [16][17][18][19].…”

Section: Modelingmentioning

confidence: 99%

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Scaling consideration on local hotspot for Si MOSFETs - for device length scale typically larger than 100 nm

Fushinobu

Yamamoto

Hatakeyama

2010

2010 12th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems

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Non-equilibrium thermal characteristics in Si MOSFETs are considered. Both lumped and rigorous electro-thermal model are deployed to examine the device lattice and electron temperatures. Non-equilibrium nature of electrons and phonons becomes important for devices with gate length typically shorter than 10 -6 m. Lumped model cannot capture the local heat generation distribution at the device level. Further discussion on the heat generation characteristics revealed that the hotspot predictions of devices typically shorter than 200 nm needs different strategy from larger devices. KEY WORDS: Si MOSFET, Length scale, NOMENCLATURE J current density, A/m 2 L gate length, m N, n, p number density, electron, hole number density, m -3 P heat dissipation rate, W q unit charge, C T temperature, K t ox oxide thickness, m V voltage, V v velocity, m/s W gate width, m x, y spatial coordinate, m Greek symbols ε 0 permeability of vacuum, F/m ε ox dielectric constant of gate oxide ε Si dielectric constant of gate oxide κ thermal conductivity ∝ mobility, m 2 /(V-s) φ potential, V Subscripts A acceptor a average in the device area D drain, donor e electron h hole G gate L lattice S source INTRODUCTIONFeature size of the current silicon MOSFETs are entering the sub-40 nm length scale, and the CMOS devices are expected to play a continuing key role in the semiconductor industries. Energy and thermal management for the CMOS devices are becoming more and more important due to the increasing demand for the energy savings of the ICT equipment. It must be pointed out that the energy and thermal management has to be considered at different length scales due to their governing physics. System level energy and thermal management including high performance cooling technology play a crucial role to control the system level temperature profile to govern the equipment design. Sub-micron scale device level energy and thermal management, on the other hand, determine two important features in operating devices: the heat dissipation and the intensity of the local hotspot (device-level temperature rise due to the self-heating.) The intensity is mainly governed by the heat generation and by the local heat conduction. It gives additional temperature rise of the devices that cannot be controlled by the system level energy and thermal management. In order to discuss the local hotspot, it is important to review the nature of heat generation, the local self-heating characteristics. Pop et al.[1] has reviewed the trend in the heat generation and transport in nanoscale transistors. Rowlette and Goodson [2] have discussed the coupling electron and phonon transport model for the heat conduction in nanoscale silicon-based devices. Phonon transport models for hotspot predictions have been reviewed by Narumanchi et al. [3]. These papers have exhibited the importance of applying Boltzmann Transport Equation (BTE)-based analysis for silicon MOSFETs with typical length smaller than 100 nm. It is shown that the hydrodynamic-based model under-predicts the local hotspot...

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Section: Modelingmentioning

confidence: 99%

“…Data for V th is taken from literature [17] to interpolate. Note that more generalized scaling approach is proposed [20], but the present analysis follows the conventional approaches.…”

Section: Modelingmentioning

confidence: 99%

Scaling consideration on local hotspot for Si MOSFETs - for device length scale typically larger than 100 nm

Fushinobu

Yamamoto

Hatakeyama

2010

2010 12th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems

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“…While little is known about their quantitative aspects, the techniques appear adequate for current fabrication technologies. However, the tolerable limit of metal concentrations is continually decreasing as the IC industry is moving toward larger wafers, possibly with lower oxygen concentrations [6], novel structures (SOI, epitaxial layers etc) and smaller device dimensions with larger electric fields and current densities [7,8]. Costly efforts are made in contamination prevention techniques, yet yield is becoming ever more sensitive to the slightest perturbations of the manufacturing environment.…”

Section: Introductionmentioning

confidence: 99%

Gettering simulator: physical basis and algorithm

Hieslmair¹,

Balasubramanian²,

Istratov³

et al. 2001

Semicond. Sci. Technol.

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The basic physical principles and mechanisms of gettering of metal impurities in silicon are well established. However, a predictive model of gettering that would enable one to determine what fraction of contaminants will be gettered in a particular process and how the existing process should be modified to optimize gettering is lacking. Predictive gettering of transition metals in silicon requires development of a robust algorithm to model diffusion and precipitation of transition metals in silicon, and material parameters to describe the kinetics of defect reactions and the stable equilibrium state of the formed complexes. This paper describes the algorithm of a gettering simulator, capable of modelling relaxation and segregation gettering of interstitially diffusing transition metal impurities in silicon wafers. The basic physical equations used to model gettering are differential equations for diffusion, precipitation and segregation. These equations are solved using the implicit finite-difference algorithm, based on the underlying physics of the problem. The material parameters required as input for the gettering simulator such as segregation coefficient, precipitation site density and precipitation radius, which need to be obtained experimentally, are briefly discussed.

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“…Device parameters are determined either by the scaling analysis (both constant field scaling and constant voltage scaling [15][16][17]), or the data taken from the literature [18][19][20][21]. In the latter analysis, scaling approach is also used to fill the unknown parameters.…”

Section: Self-consistent Lumped Electro-thermal Modelmentioning

confidence: 99%

“…In the latter analysis, scaling approach is also used to fill the unknown parameters. Data for V th is taken from literature [19] to interpolate. Note that more generalized scaling approach is proposed [22], but the present analysis follows the conventional approaches.…”

Section: Self-consistent Lumped Electro-thermal Modelmentioning

confidence: 99%

Thermal scaling consideration of Si MOSFETs with gate length typically larger than 100 nm

Fushinobu

2011

2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium

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Scaling issues in thermal behavior of silicon MOSFETs have been discussed for devices with typically larger than 100 nm. Cutting edge technologies of silicon devices are exploring the issues in deep nanometer length scales, where it is claimed that the conventional Fourier-based thermal model does not apply. It is also claimed that the BTE-based transport model is the theoretical tool to discuss the transport phenomena in sub-100 nm length scale to a certain extent of miniaturization. There however still exist unorganized thermal issues to be considered in over-100 nm regime. This research investigates the trend of thermal issues, mainly the lattice and carrier temperatures, based on the device scaling. Simple algebraic model of lattice and electron temperatures of bulk Si MOSFET is developed. Thermal behavior of the devices is discussed based on various scaling laws and actual trend. A Multi-fluid model, a full set of partial difference equations of continuum model and constitutive equations, is solved numerically to obtain the temperature distributions in the device. The results show clear threshold of the length scale where the temperature distribution and the hot spot, spatially local high temperature region, behavior changes drastically with miniaturization. Discussions show the characteristics of thermal scaling of bulk Si MOSFETs over 100 nm range. NomenclatureJ current density, A/m 2 L gate length, m N number density, m -3 n, p electron, hole number density, m -3 P heat dissipation rate, W q unit charge, C T temperature, K t ox oxide thickness, m V voltage, V v velocity, m/s W gate width, m x, y spatial coordinate, m Greek symbols H 0 permeability of vacuum, F/m H ox dielectric constant of gate oxide H Si dielectric constant of gate oxide N thermal conductivity P mobility, m 2 /(V-s) I potential, V Subscripts A acceptor a average in the device area D drain, donor e electron h hole G gate L lattice S source IntroductionFeature size of the current silicon MOSFETs are entering the sub-40 nm length scale, and the CMOS devices are expected to play a continuing key role in the semiconductor industries. Energy and thermal management for the CMOS devices are becoming more and more important due to the increasing demand for the energy savings of the ICT equipment. It must be pointed out that the energy and thermal management has to be considered at different length scales due to their governing physics. System level energy and thermal management including high performance cooling technology play a crucial role to control the system level temperature profile to govern the equipment design. Submicron scale device level energy and thermal management, on the other hand, determine two important features in operating devices: the heat dissipation and the intensity of the local hotspot (device-level temperature rise due to the self-heating.) The intensity is mainly governed by the heat generation and by the local heat conduction. It gives additional temperature rise of the devices that cannot be controlled by the system ...

show abstract

MOS technology: Trends and challenges in the ULSI era

Cited by 10 publications

References 1 publication

Scaling consideration on local hotspot for Si MOSFETs - for device length scale typically larger than 100 nm

Scaling consideration on local hotspot for Si MOSFETs - for device length scale typically larger than 100 nm

Gettering simulator: physical basis and algorithm

Thermal scaling consideration of Si MOSFETs with gate length typically larger than 100 nm

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