MOSFET carrier mobility model based on gate oxide thickness, threshold and gate voltages

Chen, Kai; Wann, H.-J.; Dunster, Jon; Ko, P.K.; Hu, Chenming; Yoshida, Makoto

doi:10.1016/0038-1101(96)00059-7

Cited by 107 publications

(28 citation statements)

References 2 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…The source of such phenomenon can be found by plotting the classical universal behaviour of effective mobility µ e f f as a function of the effective field E e f f . Figure 5 presents the result obtained using the method proposed by Niu et al [14] to extract µ e f f and the E f f expression presented by Chen et al [15]. An E −2 f f dependence of µ e f f is observed at high field.…”

Section: Mobilitymentioning

confidence: 87%

See 1 more Smart Citation

Ultimate sub-25 nm gate length NMOSFETs transport at 293 and 77 K

Bertrand

Deleonibus

Souil

et al. 2000

Superlattices and Microstructures

View full text Add to dashboard Cite

Section: Mobilitymentioning

confidence: 87%

“…µ e f f (E e f f ) characteristics at 77 K extracted on a 10 µm gate width transistors using the method presented in [14]. E e f f calculated using [15].…”

Section: Series Resistancementioning

confidence: 99%

Ultimate sub-25 nm gate length NMOSFETs transport at 293 and 77 K

Bertrand

Deleonibus

Souil

et al. 2000

Superlattices and Microstructures

View full text Add to dashboard Cite

“…Хорошо известно, что для носителей заряда в ин-версионных слоях МОП транзисторов на объемном кремнии характерна универсальная зависимость подвиж-ности от эффективного поля E eff в канале транзистора, направленного перпендикулярно плоскости индуциро-ванного канала проводимости [8,9]. Значения E eff опре-деляют распределение носителей заряда относительно гетерограницы, поэтому существует однозначная связь между E eff и доминирующим механизмом рассеяния носителей заряда.…”

Section: Introductionunclassified

“…Было показано, что для электронов в обогаще-нии зависимости µ eff (N e ) могут быть аппроксимированы степенными функциями µ eff (N e ) ∝ N −n e , где показатель n зависит от значений N e и режима пленки со стороны поверхности и, как в полевой зависимости подвижности, определяется механизмом рассеяния носителей заряда. Однако наиболее полные исследования полевых зави-симостей подвижности с идентификацией механизмов рассеяния были проведены и получены для носителей в инверсионных слоях на объемном кремнии (в стан-дартных режимах МОП транзисторов на объемном ма-териале) [5,6,8,9,12].…”

Section: Introductionunclassified

Подвижность Электронов В Инверсионных Слоях Полностью Обедняемых Пленок Кремний-На-Изоляторе

Зайцева¹,

Наумова²,

Фомин³

2017

Физика И Техника Полупроводников

View full text Add to dashboard Cite

Исследована подвижность электронов mueff в инверсионных слоях двухзатворных полностью обедняемых КНИ (кремний-на-изоляторе) МОП транзисторов в зависимости от плотности индуцированных носителей заряда Ne и температуры T при разных режимах пленки КНИ со стороны одного из затворов (инверсия-обогащение). Показано, что при большой плотности индуцированных носителей заряда (Ne>6·1012 cм-2) зависимости mueff(T) позволяют выделить компоненты подвижности mueff, связанные с рассеянием на поверхностных фононах и микрорельефе границы раздела пленка/диэлектрик. Зависимости mueff(Ne) могут быть аппроксимированы степенными функциями mueff(Ne) propto Ne-n. Определены значения показателей n зависимостей и доминирующие механизмы рассеяния электронов, индуцированных вблизи границы раздела пленки КНИ со скрытым диэлектриком, для различных интервалов Ne и режимов пленки со стороны поверхности. DOI: 10.21883/FTP.2017.04.44334.8369

show abstract

“…Under these conditions, non stationary transport can occur for very short channels and devices performances can benefit from velocity overshoot. Unless transport is limited by surface roughness or impurity scattering [4,103,104] ballistic transport can offer a new degree of freedom to the increase of devices performance in sub 100 nm Si channel length devices. If the low field mobility is high, then the mean free path of carriers becomes comparable to or higher than the channel length: ballistic transport is likely to be taken into account [49,[105][106][107].…”

Section: Exploiting Non Stationary Transport or Cmos On Semiconductormentioning

confidence: 99%

Physical and technological limitations of NanoCMOS devices to the end of the roadmap and beyond

Deleonibus

2006

Eur. Phys. J. Appl. Phys.

View full text Add to dashboard Cite

Abstract. Since the end of the last millenium, the microelectronics industry has been facing new issues as far as CMOS devices scaling is concerned. Linear scaling will be possible in the future if new materials are introduced in CMOS device structures or if new device architectures are implemented. Innovations in the electronics history have been possible because of the strong association between devices and materials research. The demand for low voltage, low power and high performance are the great challenges for the engineering of sub 50 nm gate length CMOS devices. Functional CMOS devices in the range of 5 nm channel length have been demonstrated. The alternative architectures allowing to increase devices drivability and reduce power consumption are reviewed. The issues in the field of gate stack, channel, substrate, as well as source and drain engineering are addressed. HiK gate dielectric and metal gate are among the most strategic options to consider for power consumption and low supply voltage management. By introducing new materials (Ge, diamond/graphite carbon, HiK, . . . ), Si based CMOS will be scaled beyond the ITRS as the future System-on-Chip Platform integrating also new disruptive devices. For example, the association of C-diamond with HiK, as a combination for new functionalized Buried Insulators, will bring new ways of improving short channel effects and suppress self-heating. Because of the low parasitics required to obtain high performance circuits, alternative devices will hardly compete against logic CMOS. (Fig. 1) has accelerated the scaling of CMOS devices to lower dimensions continuously despite the difficulties that appear in device optimization. PACSHowever, uncertainties about lithography, economics and physical limitations will probably slow down the evolution. For the first time, since the introduction of poly gate in CMOS devices process, showstoppers other than lithography appear to be attracting special attention and could require some breakthrough or evolution if we want to continue scaling at the same rate. Design could also be affected by this evolution.Which are the main showstoppers for CMOS scaling? In this paper, we focus on the possible solutions and guidelines for research in the next years in order to propose solutions to enhance CMOS performance before we need to skip to alternative devices. In other words, how can we offer a second life to CMOS?To that respect, the roadmap distinguishes today three types of products: High Performance (HP) (Fig. 1), Low a e-mail: sdeleonibus@cea.fr Operating Power (LOP) and Low Standby Power (LSTP) devices. In the HP case, a historical fact will happen by the 32 nm node: the contribution of static power dissipation will become higher than the dynamic power contribution to the total power consumption! This main fact could affect the MOSFET saturation current as can be observedArticle published by EDP Sciences and available at

show abstract

MOSFET carrier mobility model based on gate oxide thickness, threshold and gate voltages

Cited by 107 publications

References 2 publications

Ultimate sub-25 nm gate length NMOSFETs transport at 293 and 77 K

Ultimate sub-25 nm gate length NMOSFETs transport at 293 and 77 K

Подвижность Электронов В Инверсионных Слоях Полностью Обедняемых Пленок Кремний-На-Изоляторе

Physical and technological limitations of NanoCMOS devices to the end of the roadmap and beyond

Contact Info

Product

Resources

About