MPEG-4 video codec on an ARM core and AMBA

Park, J.H.; Kim, I.K.; Kim, S.M.; Park, Solmoi; Koo, Bontae; Shin, Kee-Young; Seo, Kwang-Deok; Cha, Jaehyuk

doi:10.1109/mpeg.2001.996457

Cited by 16 publications

(7 citation statements)

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“…It uses 3-step hierarchical search for ME with search range −32∼+31.5. In [6], it is a platform-based video codec design with ARM/AMBA. It uses a coarse ME with search range −8∼+7.5.…”

Section: Methodsmentioning

confidence: 99%

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Platform-Based MPEG-4 SOC Design for Video Communications

Chang

Chao

Hsu

et al. 2006

J VLSI Sign Process Syst Sign Image Video Technol

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An MPEG-4 video coding SOC design is presented in this paper. We adopt platform-based architecture with an embedded RISC core and efficient memory organization. A motion estimator supporting predictive diamond search and spiral full search is implemented for compromise between compression performance and design cost. The proposed data reuse scheme reduces required memory access bandwidth. For texture coding path, an interleaving DCT/IDCT scheduling with substructure sharing technique is proposed. Several key modules are integrated into an efficient platform in hardware/software co-design fashion. The cost-efficient video encoder SOC consumes 256.8 mW at 40 MHz and achieves real-time encoding of 30 CIF (352×288) frames per second.

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Section: Methodsmentioning

confidence: 99%

“…Lack of potential for future modification of advanced algorithms and higher design effort are disadvantages. Hence, some [5,6] adopted the hybrid software/hardware co-design to compromise the performance and flexibility.…”

Section: Introductionmentioning

confidence: 99%

Platform-Based MPEG-4 SOC Design for Video Communications

Chang

Chao

Hsu

et al. 2006

J VLSI Sign Process Syst Sign Image Video Technol

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“…A regular and symmetric topology, such as a mesh, fits well for dataflow type of processing with static scheduling and allocation of tasks. This is different from contemporary SoCs, such as [7] [8], that include several clock domains that are not necessarily synchronized, and some of the blocks are from time to time shut down for power saving. The overall computation is heterogeneous and still quality-of-service (QoS) in terms of guaranteed latency and/or throughput must be met for data transfers.…”

Section: Introductionmentioning

confidence: 92%

HIBI Communication Network for System-on-Chip

Salminen

Kangas

Hämäläinen

et al. 2006

J VLSI Sign Process Syst Sign Image Video Technol

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This paper presents a communication network targeted for complex system-on-chip (SoC) and network-on-chip (NoC) designs. The Heterogeneous IP Block Interconnection (HIBI) aims at maximum efficiency and minimum energy per transmitted bit combined with quality-of-service (QoS) in transfers. Other features include support for hierarchical topologies with several clock domains, flexible scalability, and runtime reconfiguration of network parameters. HIBI is intended for integrating coarse-grain components such as intellectual property (IP) blocks that have size of thousands of gates. HIBI has been implemented in VHDL and SystemC and synthesized on several CMOS technologies and on FPGA. A 32-bit wrapper requires 5400 gates and runs with 315 MHz on 0.18 μm technology which shows that only minimal area overhead is paid for the advanced features. The area and frequency results are well comparable to other NoC proposals. Furthermore, data transfers are shown to approach the maximum theoretical performance for protocol efficiency. HIBI network is accompanied with a design framework with tools for optimizing the system through automated design space exploration.

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“…As a result, there is a need for high-throughput communications links between these blocks. There exist many bus based SoCs which are widely used in industry such as AMBA [1], IBM Core Connect [2], Pi-Bus [3], etc. We know that NoC system platform as a very complex and multi-protocol networks provides end-to-end quality-of-service (QoS) is crucial for optimum system performance.…”

Section: Introductionmentioning

confidence: 99%

Improvement network-on-chip bandwidth utilization through multi protocol label switching by dividing bandwidth

Rad

Kourdy

Pooyan

et al. 2010

2010 the 2nd International Conference on Computer and Automation Engineering (ICCAE)

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we propose a combination of Mesh topology and Bisection routing in MPLS and IP network-on-chip which can increase Communication load with quality of service which is suitable for multimedia applications. We compare the performance of 2d-Mesh architectures in the sense of on chip network design methodology. The simulations of the architectures are done with two-dimensional Mesh topologies that used MPLS base recovery mechanism with bisection routing in source switch, to provide additional bandwidth for application that need more bandwidth than one link. We also carry out the high level simulation of on chip network using NS-2 to verify the analytical analysis.

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MPEG-4 video codec on an ARM core and AMBA

Cited by 16 publications

References 1 publication

Platform-Based MPEG-4 SOC Design for Video Communications

Platform-Based MPEG-4 SOC Design for Video Communications

HIBI Communication Network for System-on-Chip

Improvement network-on-chip bandwidth utilization through multi protocol label switching by dividing bandwidth

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