MPGA: an evolutionary state assignment for dynamic and leakage power reduction in FSM synthesis

Tao, Yanyun; Zhang, Yuzhen; Wang, Qinyu; Cao, Jian

doi:10.1049/iet-cdt.2016.0199

Cited by 6 publications

(1 citation statement)

References 30 publications

(58 reference statements)

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“…This task can be solved using various methods of state assignment [25][26][27]. In these methods, the number of bits in the state codes ranges from the minimum determined by formula (3) to the maximum determined by the total number of states, M. If R = M, then this is a one-hot state assignment.…”

Section: Related Workmentioning

confidence: 99%

Improving Characteristics of LUT-Based Three-Block Mealy FSMs’ Circuits

et al. 2022

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One of the very important problems connected with FPGA-based design is reducing the hardware amount in implemented circuits. In this paper, we discuss the implementation of Mealy finite state machines (FSMs) by circuits consisting of look-up tables (LUT). A method is proposed to reduce the LUT count of three-block circuits of Mealy FSMs. The method is based on finding a partition of set of internal states by classes of compatible states. To reduce the LUT count, we propose a special kind of state code, named complex state codes. The complex codes include two parts. The first part includes the binary codes of a state as the element of some partition class. The second part consists of the code of corresponding partition class. Using complex state codes allows obtaining FPGA-based FSM circuits with exactly four logic blocks. If some conditions hold, then any FSM function from the first and second blocks is implemented by a single LUT. The third level is represented as a network of multiplexers. These multiplexers generate either additional variable encoding collections of outputs or input memory functions. The fourth level generates FSM outputs. An example of synthesis and experimental results is shown and discussed. The experiments prove that the proposed approach allows reducing hardware compared to such methods as auto and one-hot of Vivado, JEDI. Further, the proposed approach produces circuits with fewer LUTs than for three-level Mealy FSMs based on joint use of several methods of structural decomposition. The experiments show that our approach allows reducing the LUT counts on average from 11 to 77 percent. As the complexity of an FSM increases, the gain from the application of the proposed method grows; the same is true for both the FSM performance and power consumption.

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Section: Related Workmentioning

confidence: 99%

Improving Characteristics of LUT-Based Three-Block Mealy FSMs’ Circuits

et al. 2022

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Reset: A Reconfigurable state encoding technique for FSM to achieve security and hardware optimality

Das

Panchanathan

2020

Microprocessors and Microsystems

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Hardware Reduction for FSMs With Extended State Codes

Barkalov,

Titarenko,

Mielcarek

et al. 2024

IEEE Access

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A method is proposed for reducing chip area occupied by logic circuits of FPGAbased Mealy finite state machines (FSMs). The proposed method aims at optimization of FSM circuits implemented with look-up table (LUT) elements of FPGA chip. The proposed method combines positive features of such state assignment methods as extended (ESCs) and composite (CSCs) state codes. The method is based on finding a partition of the set of internal states by classes of compatible states. To reduce LUT count, we propose a special kind of states codes named mixed state codes. These codes include two parts. The first part includes the maximum binary codes of states as elements of some partition class. The second part consists of the code of corresponding partition class. Unlike CSCs, the proposed approach allows obtaining partial state codes having different lengths. Unlike ESCs, all partial state codes consist of the same variables. Using mixed state codes allows obtaining LUT-based FSM circuits with exactly two levels of logic. The first level generates partial Boolean functions. The second level combines them into FSM outputs and input memory functions. If some conditions hold, then both levels consist of single-LUT circuits. Example of FSM synthesis based on mixed state codes is shown. The conducted experiments prove that the proposed approach allows reducing hardware compared with FSMs based on JEDI, one-hot state codes, CSCs and ESCs. On average, the proposed method reduces the value of LUT count by 6.21% compared to CSC-based FSMs and 22.21% compared to ESC-based counterparts. The advantages of the proposed approach grow with the growth of FSM complexness. An additional positive effect of the proposed method is a slight increase in the operating frequency.INDEX TERMS Mealy FSM, FPGA, LUT count, synthesis, extended state codes, composite state codes, mixed state codes.

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MPGA: an evolutionary state assignment for dynamic and leakage power reduction in FSM synthesis

Cited by 6 publications

References 30 publications

Improving Characteristics of LUT-Based Three-Block Mealy FSMs’ Circuits

Improving Characteristics of LUT-Based Three-Block Mealy FSMs’ Circuits

Reset: A Reconfigurable state encoding technique for FSM to achieve security and hardware optimality

Hardware Reduction for FSMs With Extended State Codes

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