MSV-Driven Floorplanning

Abstract

Abstract-Power consumption has become a crucial problem in modern circuit design. Multiple supply voltage (MSV) design is introduced to provide higher flexibility in controlling the power and performance tradeoff. One important requirement of MSV design is that timing constraints of the circuit must be satisfied after voltage assignment of the cells. In this article, we develop two algorithms to solve the voltage assignment problem under timing constraints, namely, min-cost flow (MCF) and valueoriented branch-and-bound (VOBB). In the MCF algorithm, the voltage assignment problem is formulated as a convex cost dual network flow problem, and can be solved optimally in polynomial time under certain conditions by calling a MCF solver. The VOBB algorithm, which is a VOBB-based searching method, solves the voltage assignment problem optimally in general cases by employing the MCF algorithm and a linear programming solver as subroutines. At last, we propose a MSV-driven floorplanning framework that optimizes power consumption and physical layout of a circuit simultaneously during the floorplanning stage, by embedding the MCF algorithm into a simulated annealingbased floorplanner and applying the VOBB algorithm as a postprocessing step. We compared our approach with the latest works on this problem, and the experimental results show that, using our approach, significant improvement on power saving can be achieved in much less running time, which confirms the effectiveness and efficiency of our method.

Level shifter planning for timing constrained multi-voltage SoC floorplanning

“…The algorithm is implemented in C under Linux operating system with 3.40 GHz CPU and 4 GB RAM. The benchmark suites and DP curves information are obtained from the authors of [7]. The Gurobi Optimizer [1] is employed as our ILP solver.…”

“…In terms CPU time, note that we adopt ILP method for voltage assignment, the method in [11] is almost 10X faster than us. The CPU time may be improved if the voltage assignment is operated by other techniques, such as the promising network flow based method in [7].…”

“…Considerable literature works address the multi-voltage driven SoC design problem at floorplanning stage [7,8] or post-floorplanning stage [5]. But few of them actually consider the LS placement, which makes the generated results may limit the potential applications.…”

On Mitigation of Side-Channel Attacks in 3D ICs

“…A key measure in our work is thus the management of global and local power distributions. To this end, we develop efficient algorithms for floorplanning- centric voltage assignment, a technique well-known for power management in 2D ICs [26], but so far mostly overlooked for 3D ICs. For any floorplan layout, we initially estimate the timing paths.…”

PPTP: Pre-Post Terminal Propagation in modern fixed-outline soft module VLSI floorplanning design

“…This simplifies the modern floorplanning by prioritizing the wirelength minimization. This is because the whitespace assigned can be used for other design purposes such as buffer insertion [12], level shifter positioning [13], thermal legalization, etc. Fixed-outline constraint causes modern floorplanning more difficult than conventional outline-free type, even in area-driven floorplanning [11].…”