Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding

Kim, Jangwoo; Hardavellas, Nikos; Mai, Ken; Falsafi, Babak; Hoe, James C.

doi:10.1109/micro.2007.4408256

Cited by 22 publications

(32 citation statements)

References 42 publications

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“…Decoding m data blocks n redundant blocks m+n blocks m data blocks simple coding schemes like SECDED are not practical because of the strict bound on the number of tolerable faults in each protected data chunk [7]. As technology advanced, a variety of more complex coding schemes with higher level of protection have been proposed to protect memories against MBUs [8,9,20,21].…”

Section: Encodingmentioning

confidence: 99%

“…As technology advanced, a variety of more complex coding schemes with higher level of protection have been proposed to protect memories against MBUs [8,9,20,21]. However, using sophisticated ECC techniques incurs a high overhead in terms of storage for the correction code, large latency as well as the slow and complex encoding/decoding [7,10]. In addition, another approach to reduce memory vulnerability to soft errors is to use a bit-interleaved memory with SECDED ECC to correct small-scale physically-contiguous MBUs [14,22,23].…”

Section: Encodingmentioning

confidence: 99%

“…Some schemes inspired by erasure coding have been recently proposed to protect cache memories against soft errors. A two-dimensional coding approach in which, the horizontal parity detects errors and the vertical parity corrects them, is presented in [7]. In CPPC [11], two registers are added to the cache to store the XOR of all data written to the cache and all dirty data evicted from it, respectively.…”

Section: Encodingmentioning

confidence: 99%

“…A variety of error-correction-codes (ECC) have been proposed to protect SRAM cache memories against soft errors [6][7][8][9][10][11][12]. However, the majority of existing MBU correction techniques are only able to correct a predefined number of errors per word.…”

Section: Introductionmentioning

confidence: 99%

“…The area, latency, and power overheads of these techniques exponentially grow by increasing the MBU size. Moreover, due to high complexity and overhead of ECC encoding/decoding, it is hard to implement such techniques in current processors with affordable cost [7,10]. Hence, to protect caches against MBUs, it is essential to reduce the complexity and overheads of the error protection techniques.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Protecting caches against multi-bit errors using embedded erasure coding

BanaiyanMofrad

Ebrahimi

Oboril

et al. 2015

2015 20th IEEE European Test Symposium (ETS)

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Technology scaling advancement coupled with operational and environmental effects make embedded memories more vulnerable to both manufacturing and transient errors including multi-bit upsets. Conventional error correcting codes incur high latency, area, and power overheads to correct multi-bit errors. In this paper, we propose Embedded Erasure Coding (EEC), a low-cost technique that can correct multi-bit errors with low overheads. This technique employs interleaved parity bits to provide a fast and low-cost multi-bit error detection. Using the erasure coding concept, the error correction is done by reconstructing the contents of the erroneous cache blocks within each cache set. Our proposed technique trades the performance for higher reliability by reserving a part of the cache (e.g. one way) to store the erasure codes. Our simulation results show that EEC provides high reliability (100% error detection and correction) with lower area overhead as compared to other state-ofthe-art techniques while imposing negligible performance overhead (3%). 2015 20th IEEE European Test Symposium (ETS) 978-1-4799-7603-4/15/$31.00 ©2015 IEEE ! ! ! ! ! Decoder Block P Column I/O Write Data Address Way1 Way3 Way4 Block P Block P Erasure P Read old data Old erasure Decoder Block P Column I/O Address Way1 Way2 Way3 Way4 Block P Block P Erasure P ! !

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