Multi-bit per-cell 1T SiGe Floating Body RAM for Cache Memory in Cryogenic Computing

Chakraborty, Wriddhi; Shrestha, Pragya R.; Gupta, Aniket; Saligram, R.; Spetalnick, Samuel; Campbell, J.; Raychowdhury, Arijit; Datta, Suman

doi:10.1109/vlsitechnologyandcir46769.2022.9830483

Cited by 8 publications

(4 citation statements)

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“…When the temperature increases to 77 K, ∆ID decreases over time; however, approximately 50% of ∆ID is still retained after 10 years, as indicated in Fig. 3i, much longer than the recent published memory with SiGe floating body at 77 K (8000 s) 39 .…”

Section: Mainmentioning

confidence: 72%

“…More details on the memory device characteristics with different gate lengths are presented in Figure S5. It is important to mention that, because the writing is performed at the off-state of the device, the write current through the channel is very small (Id = ~1 fA), thus an ultra-low writing power of several zJ for C 2 RAM is required, 6 orders of magnitude lower than state-of the art 1T DRAM with SiGe floating body (0.82 fJ) 39 .…”

Section: Mainmentioning

confidence: 99%

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High Storage and Energy Efficient Memory for Cryogenic Computing

Zhao,

Han,

Sun

et al. 2023

Preprint

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Efficient computing in cryogenic environments, encompassing classical von Neumann architectures, advanced quantum and neuromorphic systems, holds the potential to revolutionize big data processing. As the demand for high storage density and energy-efficient memories grows, the absence of a clear solution for cryogenic memory remains a challenge. Here, we present a cryogenic capacitorless Random Access Memory (C2RAM) utilizing advanced Si technology. This innovation is positioned to reshape cryogenic computing, with its high scalability and the capacity to be written and erased across multiple-states, significantly boosting the storage density. Notably, the C2RAM requires only ultra-low write energies, measuring just a few zeptojoules and provides exceptionally long retention times preserving data for over a decade. This positions C2RAM as a prime contender for nonvolatile memory for cryogenic von Neumann architectures and quantum technologies. In addition, the memory unit emulates biological synapses, including potentiation and depression, enabling a seamless integration into crossbar arrays, requiring no additional selectors for neuromorphic computing. The fusion of logic and analog capabilities unlocks substantial potential for high-density cryogenic memory applications. This innovative breakthrough enables the convergence of classical von Neumann, quantum, and neuromorphic computing, harnessing the significant performance advantages anticipated at cryogenic temperatures.

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Section: Mainmentioning

confidence: 72%

Section: Mainmentioning

confidence: 99%

High Storage and Energy Efficient Memory for Cryogenic Computing

Zhao,

Han,

Sun

et al. 2023

Preprint

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“…However, for deep-cryogenic (4.2 K) applications, such as superconducting computing [32], [33], [34], [35], [36], [37], [38], [39] and QC, custom embedded memories have been investigated, including static-cell designs [10], [35], [36], [39], [40], [41], [42] and dynamic-cell designs [32], [43], [44], [45], [46], [47], [48], [49], [50]. Additionally, less well-known cell designs in specific technologies have also been investigated around both 77 K [51], [52], [53] and 4.2 K [54]. Analyses based only on simulations have been attempted but do not capture the full range of cryogenic effects, e.g., not properly modeling leakage and dynamic effects [10], [41], [42], [49], [50].…”

Section: Introductionmentioning

confidence: 99%

A Benchmark of Cryo-CMOS Embedded SRAM/DRAMs in 40-nm CMOS

Damsteegt,

Overwater,

Babaie

et al. 2024

IEEE J. Solid-State Circuits

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The interface electronics needed for quantum processors require cryogenic CMOS (cryo-CMOS) embedded digital memories covering a wide range of specifications. To identify the optimum architecture for each specific application, this article presents a benchmark from room temperature (RT) down to 4.2 K of custom SRAMs/DRAMs in the same 40-nm CMOS process. To deal with the significant variations in device parameters at cryogenic temperatures, such as the increased threshold voltage, lower subthreshold leakage, and increased variability, the feasibility of different memories at cryogenic temperature is assessed and specific guidelines for cryogenic memory design are drafted. Unlike at RT, the 2T low-thresholdvoltage (LVT) DRAM at 4.2 K is up to 2× more power efficient than both SRAMs for any access rate above 75 kHz since the lower leakage increases the retention time by 40 000×, thus sharply cutting on the refresh power and showing the potential of cryo-CMOS DRAMs in cryogenic applications.

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“…The liquid nitrogen temperature (77 K) is considered by many researchers to be the most suitable temperature for massive HPC applications, because it balances the performance benefits and cost-effectiveness [3][4][5][6][7][8][9][10]. Example studies include Lee et al's proposed CryoGuard, a robust, near refresh-free DRAM operating at 77 K [8]; Byun et al's 77 K processor architecture, which demonstrated 3.4 times performance improvement [11].…”

Section: Introductionmentioning

confidence: 99%

Nonlinear behaviors in back-gate effects of FDSOI MOSFETs at cryogenic temperatures

Hu,

Ren,

Yin

et al. 2024

Semicond. Sci. Technol.

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In this work, we systematically investigate the DC performance of Fully Depleted Silicon-on-insulator (FD-SOI) MOSFETs at both room and cryogenic temperatures as low as 77 K. The influences of back-gate bias on normal and flip-well devices are measured and analyzed. Both types devices display non-linear behaviors when adjusting the back-gate voltage at cryogenic temperatures. Notably, the non-linear effects are more prominent in normal-well devices. The possible reasons are analyzed and verified by TCAD simulation, suggesting that normal-well devices are more susceptible to the formation of depletion regions between the buried oxide layer and the well. This phenomenon disrupts the linearity of the back-gate effect. This research contributes to understanding and characterizing of the back-gate effects in cryogenic environments and holds potential for high-performance computing applications.

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Multi-bit per-cell 1T SiGe Floating Body RAM for Cache Memory in Cryogenic Computing

Cited by 8 publications

References 0 publications

High Storage and Energy Efficient Memory for Cryogenic Computing

High Storage and Energy Efficient Memory for Cryogenic Computing

A Benchmark of Cryo-CMOS Embedded SRAM/DRAMs in 40-nm CMOS

Nonlinear behaviors in back-gate effects of FDSOI MOSFETs at cryogenic temperatures

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