2012 IEEE Radio Frequency Integrated Circuits Symposium 2012
DOI: 10.1109/rfic.2012.6242304
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Multi-channel 180pJ/b 2.4GHz FBAR-based receiver

Abstract: -A three-channel 2.4GHz OOK receiver is designed in 65nm CMOS and leverages MEMS to enable multiple sub-channels of operation within a band at a very low energy per received bit. The receive chain features an LNA/mixer architecture that efficiently multiplexes signal pathways without degrading the quality factor of the resonators. The single-balanced mixer and ultra-low power ring oscillator convert the signal to IF, where it is efficiently amplified to enable envelope detection. The receiver consumes a total … Show more

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Cited by 8 publications
(8 citation statements)
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“…While such system-level simplifications can decrease power consumption, they may not be sufficient to meet ULP power budget constraints. Thus, efforts have been made to further lower the power consumption in such architectures by replacing a PLL with a clever method of frequency synthesis [34][35][36], lowering the supply voltage [17,37,38], and replacing the LNA with a passive mixer front end [17]. Figure 9 shows an example of a representative FBAR-based multi-channel super-heterodyne receiver architecture [36].…”
Section: Clocked Demodulatormentioning
confidence: 99%
See 1 more Smart Citation
“…While such system-level simplifications can decrease power consumption, they may not be sufficient to meet ULP power budget constraints. Thus, efforts have been made to further lower the power consumption in such architectures by replacing a PLL with a clever method of frequency synthesis [34][35][36], lowering the supply voltage [17,37,38], and replacing the LNA with a passive mixer front end [17]. Figure 9 shows an example of a representative FBAR-based multi-channel super-heterodyne receiver architecture [36].…”
Section: Clocked Demodulatormentioning
confidence: 99%
“…Receivers are categorized into three architectures: Clocked-demodulators [13,[34][35][36][46][47][48][49][50][51][52][53][54], envelope-detectors [3,22,23,30,39,55], and super-regenerative [19,26,32,41,56,57]. Figure 17 shows that some clocked-demodulator-based receivers consume just as low power as envelope-detector-based and super-regenerative receivers by replacing a PLL with a high-Q resonator [34], or turning off the PLL during the receiver operation [13]. Figure 18 shows that super-regenerative receiver and clocked demodulator architectures attain similar levels of performance given the trade-off between sensitivity and energy-per-bit.…”
Section: Benchmarkingmentioning
confidence: 99%
“…FSK is achieved by switching between two different programming codes (i.e., frequencies), set by FSK 0[7 : 0] and FSK 1[7 : 0]. A inverter-transmission gate circuit [6] is used to create phase-matched differential signals to drive a multiplexor selecting one of FSK 0 or FSK 1 at a time.…”
Section: Circuit Designmentioning
confidence: 99%
“…Thus, there is considerable interest in minimizing the power consumption of RF circuits in such sensing nodes. Many recent publications in the area of energy-efficient RF circuits have described receivers, transmitters, and transceivers with excellent RF performance at efficiencies down to tens-to-hundreds of picojoules per bit [4]-[6]. However, such architectures are typically demonstrated and optimized for efficient performance at data rates exceeding 100 kbps.…”
Section: Introductionmentioning
confidence: 99%
“…Most recent work in low-power RF circuits describe excellent RF performance while requiring only on the order of a few tens to hundreds of picojoules to send or receive a bit of information [3]- [5]. Such radios are, however, typically optimized for sensor networks and body-area networks at data rates greater than 100 kb/s.…”
Section: Introductionmentioning
confidence: 99%