Multi-clock Soc design using protocol conversion

Abstract

Abstract

Specification Enforcing Refinement for Convertibility Verification

“…Moreover, once the existence of a converter is determined, how to synthesize it? More recently, a set of formal techniques have been proposed [1]- [5] to address these questions. Table 1 compares these approaches over a range of features.…”

“…The features listed as columns of Table 1 are: the modelling language for protocols, the language for describing desired specifications, multiple protocols (two and more than two), type of conversion algorithm, whether the approach can handle uncontrollable events, event buffering, whether data-width mismatches are handled, whether clock mismatches are handled, and finally the type of control action used. Among the proposed techniques, most approaches use Labeled Transition Systems (LTS) to describe both protocols and specifications, except [5] where CTL temporal logic is used for the specification part. Also, except the approach of [3]- [5] which use oversampling [11] to bridge clock mismatches, all other techniques ignore clock mismatches.…”

“…Among the proposed techniques, most approaches use Labeled Transition Systems (LTS) to describe both protocols and specifications, except [5] where CTL temporal logic is used for the specification part. Also, except the approach of [3]- [5] which use oversampling [11] to bridge clock mismatches, all other techniques ignore clock mismatches.…”

“…This is done using the well known idea of disabling from Discrete Event Systems (DES) control theory [12]. Here, a supervisor or controller is synthesized [3] SPA × refinement × disabling Tivoli et al [4] LTS × controlled coverability × implicit disabling Sinha et al [5] LTS CTL model-checking disabling SER Refinement LTS LTS refinement × × disabling, forcing Table 1. Features of various protocol conversion approaches to control a plant so that the controlled system (composition of the controller and the plant) satisfies the desired specification.…”

Tight WCRT analysis of synchronous C programs

“…However, it may be noted that the WCRT analysis problem developed here is essentially a safety checking problem over synchronous automata with bounded integers. Hence, this analysis may be done using a custom tool in the future to make the analysis both optimal and also to prove that the proposed analysis indeed results in tight WCRT similar in spirit to a recent model checking work on bounded integers for SoC data-exchange protocols [20].…”