Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement

Abstract

Abstract-The performance and power efficiency of multi-core processors are attractive features for safety-critical applications, as in avionics. But increased integration and average-case performance optimizations pose challenges when deploying them for such domains. In this paper we propose a novel approach to compute a interference-sensitive Worst-Case Execution Time (isWCET) considering variable accesses delays due to the concurrent use of shared resources in multi-core processors. Thereby we tackle the problem of temporal partitioning as it is required by safety-critical applications. In particular, we introduce additional phases to state-of-the-art timing analysis techniques to analyse an applications resource usage and compute an interference delay. We further complement the offline analysis with a runtime monitoring concept to enforce resource usage guarantees. The concepts are evaluated on Freescale's P4080 multi-core processor in combination with SYSGO's commercial real-time operating system PikeOS and AbsInt's timing analysis framework aiT. We abstract real applications' behavior using a representative task set of the EEMBC Autobench benchmark suite. Our results show a reduction of up to 75% of the multi-core Worst-Case Execution Time (WCET), while implementing full transparency to the temporal and functional behavior of applications, enabling the seamless integration of legacy applications.

Computing Safe Contention Bounds for Multicore Resources with Round-Robin and FIFO Arbitration

“…The derived bound, ubd m , can be used by STA as ubd by adding it compositionally to the access time to the bus considered without contention [17]. With MBTA, instead the user must determine an upper bound n r to the number of requests that the scua issues to the bus.…”

“…When the internal workings of the processor cannot be known, the ubd cannot be determined analytically, but only approximated via ubd m , as was the case in [17].…”

“…As a testimony to that, the contention behaviour of the P4080 processor has been analyzed by an avionics end-user and an STA tool provider [17] using measurements, thereby obtaining a measured approximation of the ubd [16], here denoted ubd m .…”

MC2: Multicore and Cache Analysis via Deterministic and Probabilistic Jitter Bounding

“…Other approaches make use of specific hardware and/or RTOS mechanisms to enforce precomputed bounds to the maximum contention caused/suffered at run time [27,25]. While interesting, those approaches do rely on domain-specific and custom run-time hardware mechanisms that are not typically available, and yield results that are only valid under the specific task set and system configuration.…”

Measurement-based cache representativeness on multipath programs

“…MBPTA is a probabilistic variant of MBTA that has been receiving increasing a ention since early 2000's [3,8]. We stick to the standard notion of WCET (pWCET), identifying worst-case timing bounds for tasks in isolation, disregarding inter-task and inter-core e ects: pWCET estimates computed with MBPTA hold valid by construction for multicores if hardware shared resources are MBPTA-compliant [35], or if contention in shared resources is accounted for a posteriori [7] and monitored during operation [25,26]. e vast majority of works considering MBPTA build on top of EVT.…”