Multi-layer parallel decoding algorithm and vlsi architecture for quasi-cyclic LDPC codes

Abstract

Abstract-We propose a multi-layer parallel decoding algorithm and VLSI architecture for decoding of structured quasi-cyclic low-density parity-check codes. In the conventional layered decoding algorithm, the block-rows of the parity check matrix are processed sequentially, or layer after layer. The maximum number of rows that can be simultaneously processed by the conventional layered decoder is limited to the sub-matrix size. To remove this limitation and support layer-level parallelism, we extend the conventional layered decoding algorithm and architecture to enable simultaneously processing of multiple (K) layers of a parity check matrix, which will lead to a roughly K-fold throughput increase. As a case study, we have designed a double-layer parallel LDPC decoder for the IEEE 802.11n standard. The decoder was synthesized for a TSMC 45-nm CMOS technology. With a synthesis area of 0.81 mm 2 and a maximum clock frequency of 815 MHz, the decoder achieves a maximum throughput of 3.0 Gbps at 15 iterations.

Trellis-Search Based Soft-Input Soft-Output MIMO Detector: Algorithm and VLSI Architecture

“…Nowadays, multi-Gb/s decoders, such as LDPC decoders, are feasible with reasonable complexity [35], [36]. Thus, it is very important to develop a high speed detector module to meet the overall throughput requirement of the iterative detection and decoding system.…”

A parallelized layered QC-LDPC decoder for IEEE 802.11ad

“…However, this sequential nature and the reduced number of required iterations enables LDPC decoder architectures which are based on the layered schedule to be highly efficient in terms of area and energy consumption. A multigigabit decoder based on a hybrid between a layered and a flooding schedule was presented in [4]. This multi-layered OMS decoder performs OMS decoding on K (not necessarily independent) layers simultaneously, providing a trade-off between parallelism (flooding) and convergence speed (layered).…”

“…This decoder uses the flooding schedule, which is known to have slower convergence than the layered schedule. Moreover, in [4], a multi-layered decoder for IEEE 802.11ad is presented, which effectively uses a hybrid between a layered and a flooding schedule. In both cases, parallelization has a negative effect on convergence speed.…”

Scalable communication architectures for massively parallel hardware multi-processors

“…In the past, several partially-parallel architectures have been proposed for the LDPC decoding [22,1,6,29,25,13,26,21]. However, they only deliver a throughput of a few hundreds of Mbps.…”

“…It does not solve the problem of an effective and efficient processing of the whole PCM matrix and related communication architecture for this aim. Also, some architectures for processing of only a single macro-row and a single macro-column were proposed, that required multiple local communication networks, but no global communication network [13,26,21]. However, for the demanding accelerator cases, multiple macro-rows and macro-columns have to be processed in parallel, and this requires the solution of a much more complex system of global and local communication problems.…”