Multi-level parallel clocking of CCDs for: improving charge transfer efficiency, clearing persistence, clocked anti-blooming, and generating low-noise backgrounds for pumping

Abstract

A multi-level clocking scheme has been developed to improve the parallel CTE of four-phase CCDs by suppressing the effects of traps located in the transport channel under barrier phases by inverting one of these phases throughout the transfer sequence.In parallel it was apparent that persistence following optical overload in Euclid VIS detectors would lead to undesirable signal released in subsequent rows and frames and that a suitable scheme for flushing this signal would be required. With care, the negatively biased electrodes during the multi-level transfer sequence can be made to pin the entire surface, row-by-row, and annihilate the problematic charges.This process can also be extended for use during integration to significantly reduce the unusable area of the detector, as per the clocked anti-blooming techniques developed many years ago; however, with the four-phase electrodes architecture of modern CCDs, we can take precautionary measures to avoid the problem of charge pumping and clock induced charge within the science frames.Clock induced charge is not all bad! We also propose the use of on-orbit trap-pumping for Euclid VIS to provide calibration input to ground based correction algorithms and as such a uniform, low noise background is require. Clock induced charge can be manipulated to provide a very suitable, low signal and noise background to the imaging array.Here we describe and present results of multi-level parallel clocking schemes for use in four-phase CCDs that could improve performance of high precision astronomy applications such as Euclid VIS.

Challenges in photon-starved space astronomy in a harsh radiation environment using CCDs

“…Through an understanding of how charge is stored and transferred in a CCD, built up through use of Silvaco TCAD simulations [20][21][22][23][24][25], it is possible to "encourage" trapped charge to be emitted back into the charge packet from which it was captured, as detailed in [26]. In a standard device with equal width electrodes, and assuming traps are randomly distributed, if a charge packet passes from an electrode under which a trap is present to the neighbouring electrode (as part of the standard readout of the device) then if the trap emits in the required time period, there is a 50% probability that the trap will emit the capture electron back into the charge packet from which it was captured and 50% probability into the next pixel causing a charge tail to form.…”

Mapping radiation-induced defects in CCDs through space and time

“…A flat-field of signal is integrated in the device, either through illumination or another method such as clock-induced charge [33]. If we consider the example of charge stored under phase 1 in a three-phase device as the initial position, the charge can be clocked to phase 2, phase 3, phase 1 in the neighbouring pixel and then back through phase 3, phase 2, and returning to the initial position under phase 1; this denotes one pumping cycle and is repeated (usually for a few thousand cycles).…”

The relationship between pumped traps and signal loss in buried channel CCDs

“…Multi-level clocking [3] is used during the frame dump to pin the surface and eliminate any surface trap components to the persistence. In the triangle irradiated area of the CCD273, it was found that between 1 and 40 electrons could be released into individual pixels during a 565 second dark integration.…”

“…Bias rows of ~6,000 electrons were injected into the imaging array using the Clock Induced Charge (CIC) method described in [3], between the area exposed to 55 Fe X-ray photons and the triangle irradiated area. The CIC background fills the entire imaging area and so is initially clocked forward a few rows into the dump drain and then clocked backwards to the central charge injection drain, leaving only 200 rows of bias signal in the array.…”