Multi-level Parallelism for Time- and Cost-Efficient Parallel Discrete Event Simulation on GPUs

Abstract

Abstract-Developing complex technical systems requires a systematic exploration of the given design space in order to identify optimal system configurations. However, studying the effects and interactions of even a small number of system parameters often requires an extensive number of simulation runs. This in turn results in excessive runtime demands which severely hamper thorough design space explorations.In this paper, we present a parallel discrete event simulation scheme that enables cost-and time-efficient execution of large scale parameter studies on GPUs. In order to efficiently accommodate the stream-processing paradigm of GPUs, our parallelization scheme exploits two orthogonal levels of parallelism: External parallelism among the inherently independent simulations of a parameter study and internal parallelism among independent events within each individual simulation of a parameter study. Specifically, we design an event aggregation strategy based on external parallelism that generates workloads suitable for GPUs. In addition, we define a pipelined event execution mechanism based on internal parallelism to hide the transfer latencies between host-and GPU-memory. We analyze the performance characteristics of our parallelization scheme by means of a prototype implementation and show a 25-fold performance improvement over purely CPU-based execution.

An expansion-aided synchronous conservative time management algorithm on GPU

“…Georg Kunz et al [13] propose a parallel discrete event simulation scheme that enables cost-and time-efficient execution of large scale parameter studies on GPUs. The authors explore parallelism from two orthogonal levels, external parallelism among the inherently independent simulations and internal parallelism among independent events within each individual simulation.…”

GPU accelerated three-stage execution model for event-parallel simulation

“…Many works focus on the issues in adopting the GPU platform in the applications [1,7,16,15,14,13]. The branch divergency of threads, memory hierarchy on GPU, host-device data transfer latency and global memory access pattern are mostly discussed in these works.…”

“…The branch divergency of threads, memory hierarchy on GPU, host-device data transfer latency and global memory access pattern are mostly discussed in these works. Specifically for DES on GPU, the work of Kunzmulti [7] proposes algorithms to sort and group the events according to the event type to reduce the branch divergency. A strategy to pipeline data transfer between host and device and process the data on the device side is also discussed in the work.…”

“…A typical way to handle branch divergence is to group events of the same type together and assign them to the same warp. In [7], the authors propose a sorting-and-padding algorithm as an realization of this idea. In our approach, we redefine the concept of events so that they can be processed with the same instruction.…”

Co-simulation of network infrastructure for substation automation systems

“…In the ICT field, several simulation frameworks have been developed to model large and complex network infrastructures. Some of these frameworks have the possibility to emulate the behavior of real devices, to perform the field tests of innovative algorithms [3]; in other cases, the simulation environment has been developed to optimize the computational performance, using parallel computation allowed by modern multi-cores PCs [4]. OMNeT++ network simulation framework is an ideal platform for model development, because of the flexibility of its architecture which allows an easy interface of simulator environment with external network interface (using the libpcap library) and to support parallel discrete event simulation, which can improve the computational capabilities.…”