Multi-level pass-transistor logic for low-power ULSIs

Logic synthesis for large pass transistor circuits

“…However, this approach still suffers from the BDD size problem. A multi-level pass transistor logic is introduced in [17], which tries to maximize the logic shared between different parts of the circuit by looking at the structure of a monolithic BDD. Using a monolithic BDD as the starting point and modifying its structure has two disadvantages: first, the approach will not be viable for large circuits with exponentially sized BDDs.…”

“…Each individual BDD can then be optimized by the techniques presented in this work and then mapped to a transistor-level circuit with appropriate buffering using [22]. Similarly, optimization algorithms for area, delay and power presented here can be applied to BDDs generated using [17] as well. In Section 5.2, we provide some more arguments on why, from a delay perspective for large circuits, a decomposed BDD approach is better than a monolithic BDD-based approach combined with buffer insertion.…”

SOI for digital CMOS VLSI: design considerations and advances

“…It has long been a popular circuit choice for fast arithmetic operations such as arithmetic logic unit (ALU), multiplier, and processor data-flow elements such as multiplexer, barrier shifter, etc. [38], [42]- [44]. Implementation of this low-power circuit style in the low-power SOI technology would potentially result in substantial power reduction for low-power applications.…”

“…The timing rules are therefore improved for the NAND-like (nMOS stack) and NOR-like (pFET stack) configurations. Similarly, timing rules for pass-transistor-based circuits such as CPL [42]- [44] are improved due to the lack of reverse body effect in floating-body configuration in SOI. The timing rules for some other circuit topologies, however, are degraded by the parasitic bipolar effect and the transient threshold voltage variation discussed earlier.…”

Reliable synaptic plasticity of InGaZnO transistor with TiO2 interlayer

“…However, they cannot achieve high integration density and low power consumption. Therefore, it is necessary to develop promising synaptic devices incorporating emerging materials with advanced device architectures [20,21]. InGaZnO (IGZO)-based artificial synaptic transistors have been intensively studied as the IGZO semiconductor has high field-effect mobility, lowtemperature processability, and large scalability [22][23][24][25][26].…”