To achieve high computing throughputs for data-intensive tasks in real time (e.g., autonomous driving, virtual reality, and deep learning), the development of inmemory computing (IMC) architectures is emerging as a research surge. [1,2] The key concept of IMC is the implementation of arithmetic logic units in memorybased hardware to better exploit memory bandwidth and substantially improve energy efficiency during data migration. Consequently, dynamic random access memory (DRAM)-and static random access memory (SRAM)-based IMC architectures have been widely reported. [3,4] However, these designs suffer inevitable shortcomings, such as in high standby power and long latencies caused by necessary write-back operations, which hinder their potential. Emerging nonvolatile memory (eNVM)-based IMCs, owing to their advantageous energy efficiency and compatibility with