Multi-objective optimisations for a superscalar architecture with selective value prediction

Gellért, Árpád; Calborean, Horia; Vintan, Lucian; Florea, Adrian

doi:10.1049/iet-cdt.2011.0116

Cited by 7 publications

(4 citation statements)

References 23 publications

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“…Recent improvements to FADSE, which is available as open source , allow the designer to express his or her knowledge in a human readable form using fuzzy rules .…”

Section: Methodsmentioning

confidence: 99%

Finding near‐perfect parameters for hardware and code optimizations with automatic multi‐objective design space explorations

Jahr

Calborean

Vintan

et al. 2012

Concurrency and Computation

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SummaryIn the design process of computer systems or processor architectures, typically many different parameters are exposed to configure, tune, and optimize every component of a system. For evaluations and before production, it is desirable to know the best setting for all parameters. Processing speed is no longer the only objective that needs to be optimized; power consumption, area, and so on have become very important. Thus, the best configurations have to be found in respect to multiple objectives. In this article, we use a multi‐objective design space exploration tool called Framework for Automatic Design Space Exploration (FADSE) to automatically find near‐optimal configurations in the vast design space of a processor architecture together with a tool for code optimizations and hence evaluate both automatically. As example, we use the Grid ALU Processor (GAP) and its postlink optimizer called GAPtimize, which can apply feedback‐directed and platform‐specific code optimizations. Our results show that FADSE is able to cope with both design spaces. Less than 25% of the maximal reasonable hardware effort for the scalable elements of the GAP is enough to achieve the processor's performance maximum. With a performance reduction tolerance of 10%, the necessary hardware complexity can be further reduced by about two‐thirds. The found high‐quality configurations are analyzed, exhibiting strong relationships between the parameters of the GAP, the distribution of complexity, and the total performance. These performance numbers can be improved by applying code optimizations concurrently to optimizing the hardware parameters. FADSE can find near‐optimal configurations by effectively combining and selecting parameters for hardware and code optimizations in a short time. The maximum observed speedup is 15%. With the use of code optimizations, the maximum possible reduction of the hardware resources, while sustaining the same performance level, is 50%.Copyright © 2012 John Wiley & Sons, Ltd.

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“…Recent improvements to FADSE, which is available as open source , allow the designer to express his or her knowledge in a human readable form using fuzzy rules .…”

Section: Methodsmentioning

confidence: 99%

Finding near‐perfect parameters for hardware and code optimizations with automatic multi‐objective design space explorations

Jahr

Calborean

Vintan

et al. 2012

Concurrency and Computation

View full text Add to dashboard Cite

show abstract

“…The articles [3], [4], [9] propose a new FADSE framework based on genetic algorithms. This framework takes advantage of a particularity of genetic algorithms to increase convergence speed.…”

Section: Related Workmentioning

confidence: 99%

“…Thus, we aim here to leverage works in [9], [13], [22] to tackle DSE of future many-core processors for HPC systems with the proposed A-DECA framework. It is a fully automatic approach that does not require the regular intervention of the architect to fix some choices before the exploration and then launch scripts for the exploration.…”

Section: Related Workmentioning

confidence: 99%

A-DECA: An Automated Design Space Exploration Approach for Computing Architectures to Develop Efficient High-Performance Many-Core Processors

Zaourar,

Chillet,

Philippe

2023

2023 26th Euromicro Conference on Digital System Design (DSD)

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High-performance many-core processors have complex computing architectures with many design parameters related to different levels (CPU macro/micro-architecture, interconnect, memory, specific accelerators, etc.). Design Space Exploration (DSE) is key to tackle the challenges related to the design of such processors, especially in the early stages. This work introduces A-DECA, a highly modular DSE approach for automating the exploration of design parameters. A-DECA combines simulators, models, and exploration strategies to derive relevant objective estimations while preserving a reasonable execution time. Thus, it provides a full methodology enabling the exploration of the design space in an easy-to-use, automatic, and effective way. A-DECA is evaluated in the context of next-generation HPC processors with various applications. We combine simulation tools and analytical formulations to assess PPA (Performance, Power, and Area). Based on an efficient implementation of a multi-objective genetic algorithm for the exploration strategy, current results show a great reduction of design space optimization by around 30% compared to the initial population. A-DECA optimizes the objectives and automatically returns a set of configurations with different characteristics allowing the architect to choose the best design according to the application context.

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“…If some known good individuals would have been included not at random but because of domain knowledge it would potentially help the algorithm to find good solutions faster; we introduced this approach in [26].…”

Section: Conclusion and Further Workmentioning

confidence: 99%

A Comparison of Multi-objective Algorithms for the Automatic Design Space Exploration of a Superscalar System

Calborean

Jahr

Ungerer

et al. 2013

Advances in Intelligent Systems and Computing

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Abstract. In today's computer architectures the design spaces are huge, thus making it very difficult to find optimal configurations. One way to cope with this problem is to use Automatic Design Space Exploration (ADSE) techniques. We developed the Framework for Automatic Design Space Exploration (FADSE) which is focused on microarchitectural optimizations. This framework includes several state-of-the art heuristic algorithms. In this paper we selected three of them, NSGA-II and SPEA2 as genetic algorithms as well as SMPSO as a particle swarm optimization, and compared their performance. As test case we optimize the parameters of the Grid ALU Processor (GAP) microarchitecture and then GAP together with the post-link code optimizer GAPtimize. An analysis of the simulation results shows a very good performance of all the three algorithms. SMPSO reveals the fastest convergence speed. A clear winner between NSGA-II and SPEA2 cannot be determined.

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Multi-objective optimisations for a superscalar architecture with selective value prediction

Cited by 7 publications

References 23 publications

Finding near‐perfect parameters for hardware and code optimizations with automatic multi‐objective design space explorations

Finding near‐perfect parameters for hardware and code optimizations with automatic multi‐objective design space explorations

A-DECA: An Automated Design Space Exploration Approach for Computing Architectures to Develop Efficient High-Performance Many-Core Processors

A Comparison of Multi-objective Algorithms for the Automatic Design Space Exploration of a Superscalar System

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