Multi-Poisson process analysis of real-time soft-error rate measurements in bulk 65 nm and 40 nm SRAMs

Abstract

Altitude and underground real-time soft error rate (SER) measurements on SRAM circuits have been analyzed in terms of independent multi-Poisson processes describing the occurrence of single events as a function of bit flip multiplicity. Applied for both neutron-induced and alpha particle-induced SERs, this detailed analysis highlights the respective contributions of atmospheric radiation and alpha contamination to multiple cell upset mechanisms. It also offers a simple way to predict by simulation the radiation response of a given technology for any terrestrial position, as illustrated here for bulk 65nm and 40nm SRAMs.

Real-Time Characterization of Neutron-Induced SEUs in Fusion Experiments at WEST Tokamak During D-D Plasma Operation

“…The events observed during the whole campaign (50 days = 1200 h) are the result of two radiation sources working in parallel: the natural radiation background and the artificial machine environment. For the first one, the observations nicely agree with the neutron (226 FIT/Mbit) and alpha SER (1148 FIT/Mbit) measured in a previous study [10], even if the place (altitude 250 m) and the shield situation (building roofing) slightly changed from the point-of-view of atmospheric neutrons. Indeed, the number of expected events for 1200 h of exposure to natural radiation is 226 × 3226 × (1200/10 9 ) = 0.87 ≈ 1 for atmospheric neutrons and 1148 × 3226 × (1200/10 9 ) = 4.44 ≈ 4 for chip internal radioactivity, that corresponds to a total of 5 events.…”

“…As stated in the introduction, our experiment is based on a well-known and proven RTSER testbench embedding CMOS bulk 65 nm SRAMs manufactured by STMicroelectronics, previously operating several years at altitude on the ASTEP (Altitude Single event effects Test European Platform) facility, underground at the Laboratoire Souterrain de Modane (LSM) and at sea level in Marseille [7] [8]. This experimental test equipment embeds 384 memory circuits (3,226 Gbit) manufactured by STMicroelectronics in CMOS 65 with fabrication processes based on a BPSG (Borophosphosilicate Glass)-free BEOL (Back-End-Of-Line) that eliminates the major source of 10 B in the circuits and drastically reduces the possible interaction between 10 B and very low (thermal) energy neutrons. The test chips contain 8.5 Mbit of single-port SRAM (without deep-Nwell) with a bit cell area of 0.525 µm 2 .…”

“…The ensemble of the circuits was controlled and monitored using a high reliability FPGA-based tester and characterized several years at altitude, underground and at sea level. Details about the setup and previous RTSER experiments can be found in [10]. We recall here that our RTSER testbench is fully compliant with all the specifications of the Joint Electron Device Engineering Council (JEDEC) standard JESD89B [11].…”

“…All measurements have been conducted under nominal conditions: supply voltage of 1.2V, room temperature, checkerboard test pattern. Just before this work, the equipment has been continuously working since March 2015 in Marseille (sea level), showing a consolidated and stable soft-error rate equal to n-SER = 226 FIT/Mbit due to atmospheric neutrons (NYC conditions) and α-SER = 1148 FIT/Mbit due to internal chip radioactivity [10].…”

Fusion Neutron-Induced Soft Errors During Long Pulse D–D Plasma Discharges in the WEST Tokamak

“…Fig. 8 shows bit flip distributions obtained by numerical simulation [21] for different D-T/D-D neutron fluence ratios ranging from 0% to 5 %. These simulations are based on a multi-Poisson process describing the occurrence of SBUs and MCUs as independent Poisson processes running in parallel with distinct event rates estimated from previous results.…”