Multi-shaped beam: development status and update on lithography results

Slodowski, Matthias; Doering, Hans-Joachim; Dorl, Wolfgang; Stolberg, Ines A.

doi:10.1117/12.879446

Cited by 8 publications

(8 citation statements)

References 5 publications

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“…However, the integration of this advanced patterning technology into current complex CMOS manufacturing processes is still challenging. The low throughput of current single e-Beam tools limits high volume manufacturing applications and multiple beam systems are still not mature [1]- [2]. The process of multi beam exposures can be emulated by single beam technologies available in the field.…”

Section: Introductionmentioning

confidence: 99%

“…The low throughput of today's single e-Beam tools limits high volume manufacturing applications and maturity of parallel (multi) beam systems is still insufficient [1,2]. Additional concerns like transistor or material damage of underlying layers during exposure at high electron density or acceleration voltage have to be addressed for advanced technology nodes.…”

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confidence: 99%

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Verification of E-Beam direct write integration into 28nm BEOL SRAM technology

Hohle¹,

Choi²,

Gutsch³

et al. 2015

SPIE Proceedings

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Electron beam direct write lithography (EBDW) potentially offers advantages for low-volume semiconductor manufacturing, rapid prototyping or design verification due to its high flexibility without the need of costly masks. However, the integration of this advanced patterning technology into complex CMOS manufacturing processes remains challenging. The low throughput of today’s single e-Beam tools limits high volume manufacturing applications and maturity of parallel (multi) beam systems is still insufficient [1,2]. Additional concerns like transistor or material damage of underlying layers during exposure at high electron density or acceleration voltage have to be addressed for advanced technology nodes. In the past we successfully proved that potential degradation effects of high-k materials or ULK shrink can be neglected and were excluded by demonstrating integrated electrical results of 28nm node transistor and BEOL performance following 50kV electron beam dry exposure [3]. Here we will give an update on the integration of EBDW in the 300mm CMOS manufacturing processes of advanced integrated circuits at the 28nm SRAM node of GLOBALFOUNDRIES Dresden. The work is an update to what has been previously published [4]. E-beam patterning results of BEOL full chip metal and via layers with a dual damascene integration scheme using a 50kV VISTEC SB3050DW variable shaped electron beam direct writer at Fraunhofer IPMSCNT are demonstrated. For the patterning of the Metal layer a Mix & Match concept based on the sequence litho - etch -litho -etch (LELE) was developed and evaluated wherein several exposure fields were blanked out during the optical exposure. Etch results are shown and compared to the POR. Results are also shown on overlay performance and optimized e-Beam exposure time using most advanced data prep solutions and resist processes. The patterning results have been verified using fully integrated electrical measurement of metal lines and vias on wafer level. In summary we demonstrate the integration capability of EBDW into a productive CMOS process flow at the example of the 28nm SRAM technology node

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Section: Introductionmentioning

confidence: 99%

mentioning

confidence: 99%

Verification of E-Beam direct write integration into 28nm BEOL SRAM technology

Hohle¹,

Choi²,

Gutsch³

et al. 2015

SPIE Proceedings

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“…An arrangement of Multi Deflection Arrays (MDA) allows operation with multiple shaped beams of variable size, which can be deflected and controlled individually. Details of the approach were already disclosed on various occasions [2,3,5]. Specific optimizations of the Electron Optical Column (EOC) are ongoing to fully adapt MSB to future industry's requirements.…”

Section: Introductionmentioning

confidence: 99%

“…The previously presented Multi Shaped Beam (MSB) approach [2,3] is considered a potential solution for high throughput mask write application. In order to fully adapt the MSB concept to future industry's requirements specific optimizations are planned.…”

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confidence: 99%

Optimization of MSB for future technology nodes

Doering

Elster

Klein

et al. 2012

Alternative Lithographic Technologies IV

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In the ITRS roadmap [1] increasingly long mask write and cycle time is explicitly addressed as a difficult challenge in mask fabrication for the 16nm technology node and beyond. Write time reduction demands have to be seen in relation to corresponding performance parameters like Line Width Roughness (LWR), resolution, placement as well as CD Uniformity.The previously presented Multi Shaped Beam (MSB) approach [2, 3] is considered a potential solution for high throughput mask write application. In order to fully adapt the MSB concept to future industry's requirements specific optimizations are planned.The key element for achieving write time reduction is a higher probe current at the target, which can be obtained by increasing the number of beamlets as well as applying a higher current density. In the present paper the approach of a 256 beamlet MSB design will be discussed. For a given image field size along with a beamlet number increase both beamlet pitch and size have to be optimized. Out of previous investigations, one finding was that by changing the demagnification after the beam forming section of the MSB column the overall performance can be optimized. Based on first electron-optical simulations for a new final lens a larger demagnification turned out to be advantageous. Stochastic beam blur simulation results for the MSB reduction optics will be presented. During the exposure of a pattern layout the number of used beams, their shape and their distribution within the image field varies, which can lead to space charge distortion effects. In regard to this MSB simulation results obtained for an image field of approximately 10x10µm² will be presented. For the 256 beamlet MSB design and resist sensitivities of 20µC/cm², 40µC/cm² and 100µC/cm² write time and LWR simulations have been performed. For MSB pattern data fracturing an optimized algorithm has been used, which increased the beamlet utilization factor (indicates the mean number of beamlets which are used per multi-shot). Finally an update with regard to the required changes of the data path architecture for the 256 beamlet MSB approach will be given. Data integrity as an important aspect of the production worthiness of such a systems will be discussed specifically.

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“…Even Variable Shaped Beam (VSB) tools and the use of cell projection (CP) require exposure times of more than a day per 300mm wafer. True Maskless Litho (ML2) using massively parallelization of beams proposed by companies like MAPPER Lithography [4], IMS Nanofabrication [5], Vistec Electron Beam [6], KLA Tencor [7], Multibeam [8] or Advantest [9] is currently being developed but still several years away from full mass manufacturing. Optical lithography using 193nm immersion on the other hand is now moving towards the 28nm mass manufacturing node and beyond by applying costly multiple patterning solutions such as self-aligned or spacer assisted double patterning (SADP) [10] or sophisticated exposure technologies like source-mask optimization (SMO) or inverse lithography.…”

Section: Introductionmentioning

confidence: 99%

Feasibility study of optical/e-beam complementary lithography

Hohle¹,

Choi²,

Freitag³

et al. 2012

Alternative Lithographic Technologies IV

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Using electron beam direct write (EBDW) as a complementary approach together with standard optical lithography at 193nm or EUV wavelength has been proposed only lately and might be a reasonable solution for low volume CMOS manufacturing and special applications as well as design rule restrictions. Here, the high throughput of the optical litho can be combined with the high resolution and the high flexibility of the e-beam by using a mix & match approach (Litho- Etch-Litho-Etch, LELE). Complementary Lithography is mainly driven by special design requirements for unidirectional (1-D gridded) Manhattan type design layouts that enable scaling of advanced logic chips. This requires significant data prep efforts such as layout splitting. In this paper we will show recent results of Complementary Lithography using 193nm immersion generated 50nm lines/space pattern addressing the 32nm logic technology node that were cut with electron beam direct write. Regular lines and space arrays were patterned at GLOBALFOUNDRIES Dresden and have been cut in predefined areas using a VISTEC SB3050DW e-beam direct writer (50KV Variable Shaped Beam) at Fraunhofer Center Nanoelectronic Technologies (CNT), Dresden, as well as on the PML2 tool at IMS Nanofabrication, Vienna. Two types of e-beam resists were used for the cut exposure. Integration issues as well as overlay requirements and performance improvements necessary for this mix & match approach will be discussed

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Multi-shaped beam: development status and update on lithography results

Cited by 8 publications

References 5 publications

Verification of E-Beam direct write integration into 28nm BEOL SRAM technology

Verification of E-Beam direct write integration into 28nm BEOL SRAM technology

Optimization of MSB for future technology nodes

Feasibility study of optical/e-beam complementary lithography

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