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While significant resources are invested in bringing EUV lithography to the market, multi electron beam direct patterning is still being considered as an alternative or complementary approach for patterning of advanced technology nodes. The possible introduction of direct write technology into an advanced process flow however may lead to new challenges. For example, the impact of high-energy electrons on dielectric materials and devices may lead to changes in the electrical parameters of the circuit compared to parts conventionally exposed by optical lithography. Furthermore, degradation of product reliability may occur. These questions have not yet been clarified in detail. For this study, pre-structured 300mm wafers with a 28nm BEOL stack were dry-exposed at various processing levels using a 50kV variable shaped e-beam direct writer. The electrical parameters of exposed structures were compared to non-exposed structures. The data of line resistance, capacitance, and line to line leakage were found to be within the typical distributions of the standard process. The dielectric breakdown voltages were also comparable between the splits, suggesting no dramatic TDDB performance degradation. With respect to high-k metal gate transistor parameters, a decrease in threshold voltage shift sensitivity was observed as well as a reduced sensitivity to hot carrier injection. More detailed investigations are needed to determine how these findings need to be considered and whether they represent a risk for the introduction of maskless lithography into the process flow of advanced technology nodes

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