Multi stage OTA design: From matrix description to circuit realization

Biabanifard, Sadegh; Hosseini, Seyede Marzieh; Biabanifard, Mohammad; Asadi, Shahrouz; Yagoub, M.C.E.

doi:10.1016/j.mejo.2018.05.007

Cited by 35 publications

(36 citation statements)

References 24 publications

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“…High‐gain multistage amplifiers are preferred over single‐stage configurations in modern mixed‐signal processing modules with stringent accuracy requirement . These amplifiers ensure that maximum signal dynamic range is achieved under the low‐voltage supply of short‐channel metal‐oxide semiconductor (MOS) transistors since the output stage can be implemented by two transistors only.…”

Section: Introductionmentioning

confidence: 99%

Global impedance attenuation network for multistage OTAs driving a broad range of load capacitor

Aminzadeh

Valinezhad

Grasso

2020

Circuit Theory & Apps

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Summary Advanced multistage amplifiers suffer from load‐dependent stability issues, which limit the load capacitor range they can drive. In this work, the concept of global impedance attenuation (GIA) network is introduced to improve an amplifier's stability in the presence of significant load capacitor variations. Composed of multiple parallel resistor‐capacitor (RC) branches, the equivalent high‐frequency output impedance of gain stages is shaped by the GIA network such that a desired frequency spectrum is obtained over a wide range of load capacitor. The parasitic poles at the output of the gain stages are nullified by the proposed network, thereby simplifying the amplifier's transfer function and reducing the minimum load capacitor it can drive. The idea is applied to design a three‐stage operational transconductance amplifier (OTA) with cascode global impedance attenuation (CGIA). Small‐signal analysis shows that the OTA is stable regardless of the load capacitor, and it can drive very small to ultra‐large load capacitors. This feature is verified by the post‐layout simulations of a CGIA amplifier in 0.18‐μm complementary metal‐oxide semiconductor (CMOS) process. The core occupies a die area of 0.0053 mm2 while consuming a static current of 10.97 μA from 1.8‐V voltage supply. The unity‐feedback configuration is unconditionally stable for any load capacitor higher than 10 pF. To the best of our knowledge, this corresponds to the widest range of load capacitance reported for prior‐art three‐stage amplifiers.

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Section: Introductionmentioning

confidence: 99%

Global impedance attenuation network for multistage OTAs driving a broad range of load capacitor

Aminzadeh

Valinezhad

Grasso

2020

Circuit Theory & Apps

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“…We need therefore to know how much accuracy is needed for a specific application in order to interpret with confidence the extent to which statements considered as a valid deliberation. Generally, the discussed range of target frequency is from DC frequency to GBW frequency; hence, the estimated transfer function is accurate enough if shows compatible response just in the mentioned frequency range …”

Section: Introductionmentioning

confidence: 99%

“…Generally, the discussed range of target frequency is from DC frequency to GBW frequency; hence, the estimated transfer function is accurate enough if shows compatible response just in the mentioned frequency range. 18 To build up a better picture of frequency compensation appreciably requires to consider Miller effect as a main cause to pole-zero positioning. Much of the potential for most of previous structures lay in exploiting Miller effect.…”

mentioning

confidence: 99%

A high‐performance CMOS four‐stage amplifier

Zanjani

Asiyabi

Biabanifard³

2019

Int J Numerical Modelling

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In this paper, we theoretically propose and mathematically describe an effective four‐stage structure in Complementary metal‐oxide‐semiconductor (CMOS) technology based on differential block feedback. The special architecture of frequency compensation network improves frequency response with very small value of compensation capacitor, which results in low die area occupation. The presented novel and simple four‐stage structure is frequency compensated just via single Miller capacitor and a differential block. Symbolical transfer function is calculated, and circuit dynamics are introduced. To well explain theoretical description, the proposed configuration at circuit level is simulated using Taiwan Semiconductor Manufacturing Company Limited (TSMC) 0.18‐μm CMOS technology and HSPICE circuit simulator. The proposed configuration and corresponding circuit benefits from circuit simplicity and low die‐area occupation. The frequency compensation network forms two Miller loops with negative loop gains. Feedback paths are amplified via differential block while feedforward paths are attenuated, leads to improving frequency response compare with conventional structures. Ample simulation results are in good agreement with theoretical description. Leveraging the concept and method proposed four‐stage amplifier exhibits 170 dB, 8.12 MHz, and 90° as direct current (DC) gain, Gain‐BandWidth Product (GBW), and Pase Margin (PM), respectively. The supply voltage is set to 1.8 V, while the simulated circuit consumes 380 μW.

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“…Finally, ACBC is known as one of the best techniques for frequency compensation. In this method, the second‐stage gain is increased in high frequency, therefore, improving the overall frequency response of an OTA [9, 14, 16‐35] …”

Section: Introductionmentioning

confidence: 99%

“…In this method, the second-stage gain is increased in high frequency, therefore, improving the overall frequency response of an OTA [9,14,[16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35]. 9,14,[16][17][18][19][20][21][22] In this article, a new compensation technique is proposed. It uses a fully differential feedback path to remove the feedforward path and enhance the frequency response regarding PM and GBW.…”

Section: Introductionmentioning

confidence: 99%

Multistage operational transconductance amplifier frequency compensation technique based on fully differential feedback stage

Zanjani

Khatib

Chabok

2019

Int J Numerical Modelling

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In this article, a new configuration of a three-stage Complementary metaloxide-semiconductor (CMOS) operational transconductance amplifier (OTA) isproposed. It removes the feedforward path while simultaneously amplifying the feedback path in the compensation network. Also, the proposed circuit uses only one small compensation capacitor which makes it appropriate regarding die area. The approach behind is demonstrated through a successful design using 0.18-μm CMOS technology. In fact, the simulated OTA shows better performance in comparison with other methods and achieved 20.2 MHz, 82 , and 124 dB as gain-bandwidth product, phase margin, and DC gain, respectively, and consumes 545 μW @ 1.8 V. K E Y W O R D S

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Multi stage OTA design: From matrix description to circuit realization

Cited by 35 publications

References 24 publications

Global impedance attenuation network for multistage OTAs driving a broad range of load capacitor

Global impedance attenuation network for multistage OTAs driving a broad range of load capacitor

A high‐performance CMOS four‐stage amplifier

Multistage operational transconductance amplifier frequency compensation technique based on fully differential feedback stage

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