Multi-TAP architecture for IP core testing and debugging on network-on-chip

Abstract

With the trend to deep-sub-micron (DSM) technology, the ability for post-fabrication testing has become a big concern for system-on-chip (SoC) designers. The testing problem of network-based SoCs is categorized into two major parts, intellectual property (IP) core testing and communication infrastructure testing. This paper presents an IP testing platform using multiple-test-access-port (multi-TAP) for mesh-based networkon-chip (NoC). In our approach, the TAP ports of IPs are connected together in a daisy chain. In addition, IEEE 1149.1 standard (JTAG) is used to connect TAPs of IPs to the external tester. The proposed platform provides comprehensive testing and debugging for each individual IP without incurring dependency to other IPs. The main advantage of the proposed platform is the ability to bypass the IPs which are not involved in the process of testing. Hence, It reduces the required number of clock cycles to send test vectors to the IP/IPs under test.

A New Approach to Model the Effect of Topology on Testing Using Boundary Scan

“…The authors of [17] proposed a Built-in Self Test (BIST)-based boundary scan architecture to at-speed test of cross talk faults for inter-switch communication links (interconnection between two nodes) in NoC. At the end of the paper, the number of clocks is calculated using a [20]. Chakrabarty and Goel et al [10] presented two lower bound formulations for SoC testing time models when dedicated bus-based Test Access Mechanism (TAM) is used.…”