Multi-Threshold NULL Convention Logic (MTNCL): An  Ultra-Low Power Asynchronous Circuit Design Methodology

Zhou, Liang; Parameswaran, Roshini; Parsan, Farhad A.; Smith, Scott C.; Di, Jia

doi:10.3390/jlpea5020081

Cited by 34 publications

(15 citation statements)

References 18 publications

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“…The next section discusses the existing AFPA architecture proposed by Noche and Jose [133], Sheikh and Manohar [134][135][136], and Jun and Wang [115], and these are the only designs available in literature that discusses the implementation of AFPA architecture. The MTNCL approach discussed in [137] does not provide any details on implementing the AFPA; however, this paper is included for the review since it provides the performance comparison of floating-point addition/subtraction operations for both synchronous and asynchronous floating-point co-processor.…”

Section: Asynchronous Floating-point Addersmentioning

confidence: 99%

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Asynchronous Floating-Point Adders and Communication Protocols: A Survey

2020

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Addition is the key operation in digital systems, and floating-point adder (FPA) is frequently used for real number addition because floating-point representation provides a large dynamic range. Most of the existing FPA designs are synchronous and their activities are coordinated by clock signal(s). However, technology scaling has imposed several challenges like clock skew, clock distribution, etc., on synchronous design due to presence of clock signal(s). Asynchronous design is an alternate approach to eliminate these challenges imposed by the clock, as it replaces the global clock with handshaking signals and utilizes a communication protocol to indicate the completion of activities. Bundled data and dual-rail coding are the most common communication protocols used in asynchronous design. All existing asynchronous floating-point adder (AFPA) designs utilize dual-rail coding for completion detection, as it allows the circuit to acknowledge as soon as the computation is done; while bundled data and synchronous designs utilizing single-rail encoding will have to wait for the worst-case delay irrespective of the actual completion time. This paper reviews all the existing AFPA designs and examines the effects of the selected communication protocol on its performance. It also discusses the probable outcome of AFPA designed using protocols other than dual-rail coding.

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Section: Asynchronous Floating-point Addersmentioning

confidence: 99%

“…Liang et al [137] have proposed a Multi-Threshold NULL Convention Logic (MTNCL) or Sleep Convention Logic (SCL), which is a combination of Multi-Threshold CMOS (MTCMOS) with NULL Convention Logic (NCL). MTCMOS is designed using transistors with different threshold voltages (V t ) viz.…”

Section: Multi-threshold Null Convention Logic (Mtncl)mentioning

confidence: 99%

Asynchronous Floating-Point Adders and Communication Protocols: A Survey

2020

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“…The basic Null Convention Logic design enables robust, self timed asynchronous circuit comprising of SET, RESET, Hold0 and Hold1 blocks as shown in Fig.1 [7,11,12]. Employing multi-threshold to NCL [11,13] technique results with the reduced transistor count in less circuit area and reduced power consumption. The MTNCL circuit design with a little high threshold voltage (V th ) transistor is presented in Fig.…”

Section: A Multi-threshold Null Convention Logic (Mtncl)mentioning

confidence: 99%

Sense Amplifier Half Buffer Based Ripple Carry Adder for IEEE 754 Standards

Rongali,

Jyothula

2020

IJEAT

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Addition is a specifically used indispensable computation used for most of the applications including digital systems and control systems. Adder is a primitive constituent used in the construction of digital IC; also it is an essential part of signal processing applications like DSP. The speed of an adder circuit holds a considerable influence on the total performance of digital circuits. The prime objective of this research is to design ripple carry adder using different asynchronous logics like Multithreshold null convention logic (MTNCL), Multi-threshold dual spacer dual rail delay insensitive logic (MTD 3 L) and proposed Sense amplifier half buffer logic (SAHB). SAHB is an asynchronous Quasi-Delay -Insensitive (QDI) method used to achieve significant functional speed of the circuit. The standard library cells (2-input AND/NAND, 2-input OR/NOR, 2-input XOR/XNOR) are designed using proposed SAHB logic to design an 8-bit Ripple Carry Adder circuit. The proposed SAHB logic design provides the solution of minimum delay with improved speed compared to the existing logic design techniques. The asynchronous logics are designed using mentor graphics tool with 130nm technology. Various performances attributes like power dissipation, delay and energy are tabulated and compared with existing logics.

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“…Multi-Threshold NULL Convention Logic (MTNCL) [7][8][9][10][11][12][13][14][15] is created by implementing MTCMOS power-gating in NCL. MTNCL uses both Low-V t and High-V t transistors and introduces a sleep function that replaces the functionality of hysteresis.…”

Section: Asynchronous Circuitsmentioning

confidence: 99%

Voltage Stacking for Simplifying Power Management in Asynchronous Circuits

Suchanek

Zhong

2018

VLSICS

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Multiple power domains on a single integrated circuit (IC) are becoming more common due to the increasing complexity of systems on chips (SoCs) as process nodes continue to get smaller. Supplying the correct voltage to each domain requires the use of multiple voltage converters that occupy substantial space either on-chip or off-chip and introduce additional power loss in the conversions. In this paper, an asynchronous paradigm called Multi-Threshold NULL Convention Logic (MTNCL) is used to create a "stacked" architecture that reduces the number of converters needed and thereby mitigating the aforementioned problems. In this architecture, the MTNCL circuits are stacked between a multiple of V DD and GND, where simple control mechanisms alleviate the induced dynamic range fluctuation problem. The GLOBALFOUNDRIES 32nm Silicon-on-Insulator (SOI) CMOS process is used to evaluate and analyze the theoretical effects of parasitic extracted physical implementations in stacking different circuits running different workloads. These results show that the "stacked" architecture introduce negligible overhead compared to the operation of the individual circuits while substantially alleviating the need for voltage converters, which in turn reduces the overall power consumption of the system.

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Multi-Threshold NULL Convention Logic (MTNCL): An Ultra-Low Power Asynchronous Circuit Design Methodology

Cited by 34 publications

References 18 publications

Asynchronous Floating-Point Adders and Communication Protocols: A Survey

Asynchronous Floating-Point Adders and Communication Protocols: A Survey

Sense Amplifier Half Buffer Based Ripple Carry Adder for IEEE 754 Standards

Voltage Stacking for Simplifying Power Management in Asynchronous Circuits

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