This paper develops an ultra-low power asynchronous circuit design methodology, called Multi-Threshold NULL Convention Logic (MTNCL), also known as Sleep Convention Logic (SCL), which combines Multi-Threshold CMOS (MTCMOS) with NULL Convention Logic (NCL), to yield significant power reduction without any of the drawbacks of applying MTCMOS to synchronous circuits. In contrast to other power reduction techniques that usually result in large area overhead, MTNCL circuits are actually smaller than their original NCL versions. MTNCL utilizes high-Vt transistors to gate power and ground of a low-Vt logic block to provide for both fast switching and very low leakage power when idle. To demonstrate the advantages of MTNCL, a number of 32-bit IEEE single-precision floating-point co-processors were designed for comparison using the 1.2 V IBM 8RF-LM 130 nm CMOS process: original NCL, MTNCL with just combinational logic (C/L) slept, Bit-Wise MTNCL (BWMTNCL), MTNCL with C/L and completion logic slept, MTNCL with C/L, completion logic, and registers slept, MTNCL with Safe Sleep architecture, and synchronous MTCMOS. These designs are compared in terms of throughput, area, dynamic

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In this paper, passive Intelligent Reflecting Surface (IRS) is used to enhance the performance of a Full Duplex (FD) bidirectional Machine Type Communication (MTC) system with two source nodes. Each node is equipped with two antennas to operate in FD mode. In reality, self-interference and discrete phase shifting are two major impairments in FD and IRS-assisted communication, respectively. The self-interference at source nodes operating in FD mode is mitigated by increasing the number of meta-surface elements at the IRS. Bit Error Rate (BER) and outage performances are analyzed with continuous phase shifting and discrete phase shifting in IRS. Closed-form analytical expressions are derived for the outage probability and BER performances of the IRS-assisted bidirectional FD-MTC system with a continuous phase shifter. The outage and BER performances of the IRS-assisted bidirectional MTC system in the FD mode have Signal-to-Noise Ratio (SNR) improvement compared with the IRS-assisted bidirectional MTC system in Half Duplex (HD) mode, as the number of reflecting elements in IRS is doubled in the FD mode. The outage and BER performances are degraded by a discrete phase shifter. Hence, performance degradation of the proposed IRS-assisted bidirectional FD-MTC is examined for 1-bit shifter (0, π), 2-bit shifter (0, π/2, π, 3π/2), and for 3-bit shifter (0, π/4, π/2, 3π/4, π, 5π/4, 3π/2, 7π/4). The performance degradation when a discrete phase shifter is employed in IRS is compared with the ideal continuous phase shifter in IRS. Further, achievable rate analysis is carried out for finding the best location of the IRS in a bidirectional FD-MTC system.

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