Multi-tier $\mathrm{N}=4$ Binary Stacking, combining Face-to-Face and Back-to-Back Hybrid Wafer-to-Wafer Bonding Technology

Huylenbroeck, Stefaan Van; Vos, Joeri De; Teugels, Lieve; Iacovo, Serena; Fodor, Ferenc; Miller, Andy; Plas, G. Van der; Beyer, Gerald; Beyne, Eric

doi:10.1109/ectc32696.2021.00173

Cited by 7 publications

(1 citation statement)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Current hybrid-bonding technologies for imagers are currently limited to two layers [1], while advanced hybrid bonding and TSVs integration was presented but not yet closely assembled togather [3,4]. Regarding the design for 3D pitches below 1µm, available CAD tools are not able to address it efficiently, current design solutions consists in tricking existing 2D place & route tools but still requiring separate placements [7].…”

Section: Introductionmentioning

confidence: 99%

Advanced 3d Design and Technologies for 3-Layer Smart Imager

Vivet

Arnaud

Borel

et al. 2022

2022 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)

View full text Add to dashboard Cite

CMOS Imagers have adopted 3D integration using Back-Side Illumination (BSI) technology, with 2 CMOS layers assembled using Wafer-to-Wafer and advanced Hybrid Bonding technology. Targeting innovative AI and Machine Learning application, for offering AI processing at the edge within the image sensor itself, this paper presents some new 3D design and technology solutions in order to build a 3-layer Smart Imager. The hybrid bonding technology for assembly of multi wafers with a capability below 1 µm pitch is shown as well as Through Silicon Via (TSV) of 2 µm pitch compatible with hybrid bonding. To offer Design Technology Co-Optimization (DTCO) capabilities, a Place & Route methodology is proposed with the associated PDKIT to benefit of fine pitch interconnects.

show abstract